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* [SelectionDAG] rename/move isKnownToBeAPowerOfTwo() from TargetLowering (NFC)Sanjay Patel2016-05-192-32/+30
| | | | | | | | | There are at least 2 places (DAGCombiner, X86ISelLowering) where this could be used instead of ad-hoc and watered down code that is trying to match a power-of-2 pattern. Differential Revision: http://reviews.llvm.org/D20439 llvm-svn: 270073
* [LAA] Check independence of strided accesses before forward caseMatthew Simpson2016-05-191-10/+11
| | | | | | | | | | | | This patch changes the order in which we attempt to prove the independence of strided accesses. We previously did this after we knew the dependence distance was positive. With this change, we check for independence before handling the negative distance case. The patch prevents LAA from reporting forward dependences for independent strided accesses. This change was requested in the review of D19984. llvm-svn: 270072
* [llvm-mc] - Teach llvm-mc to generate compressed debug sections in zlib style.George Rimar2016-05-192-39/+21
| | | | | | | | | | | | Before this patch llvm-mc generated zlib-gnu styled sections. That means no SHF_COMPRESSED flag was set, magic 'zlib' signature was used in combination with full size field. Sections were renamed to "*.z*". This patch reimplements the compression style to zlib one as zlib-gnu looks to be depricated everywhere. Differential revision: http://reviews.llvm.org/D20331 llvm-svn: 270070
* [AArch64 ] Generate a BFXIL from 'or (and X, Mask0Imm),(and Y, Mask1Imm)'.Chad Rosier2016-05-191-0/+59
| | | | | | | | | | | | | | | | | | Mask0Imm and ~Mask1Imm must be equivalent and one of the MaskImms is a shifted mask (e.g., 0x000ffff0). Both 'and's must have a single use. This changes code like: and w8, w0, #0xffff000f and w9, w1, #0x0000fff0 orr w0, w9, w8 into lsr w8, w1, #4 bfi w0, w8, #4, #12 llvm-svn: 270063
* Test commit.Ranjeet Singh2016-05-191-1/+1
| | | | llvm-svn: 270056
* [AMDGPU][llvm-mc] Fixes to support buffer atomics.Artem Tamazov2016-05-192-11/+88
| | | | | | | | | | | | Fixes for MUBUF_Atomic instructions to make operand list valid: - For RTN insns, make a copy of $vdata_in operand as $vdata. - Do not add operand for GLC, it is hardcoded and comes as a token. Workaround to avoid adding multiple default optional operands. Tests added. Differential Revision: http://reviews.llvm.org/D20257 llvm-svn: 270049
* ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocationZoran Jovanovic2016-05-194-3/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D15526 llvm-svn: 270048
* [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine ↵Daniel Sanders2016-05-191-1/+1
| | | | | | | | | | | | | | verifier. Summary: Partially fixes PR27458 Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20330 llvm-svn: 270037
* [X86] Enable RRL part of the LEA optimization pass for -O2.Andrey Turetskiy2016-05-191-10/+8
| | | | | | | | | | Enable "Remove Redundant LEAs" part of the LEA optimization pass for -O2. This gives 6.4% performance improve on Broadwell on nnet benchmark from Coremark-pro. There is no significant effect on other benchmarks (Geekbench, Spec2000, Spec2006). Differential Revision: http://reviews.llvm.org/D19659 llvm-svn: 270036
* [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructionsZlatko Buljan2016-05-194-4/+55
| | | | | | Differential Revision: http://reviews.llvm.org/D18352 llvm-svn: 270030
* [X86] Generalize and combine some similar type constraints and node types. ↵Craig Topper2016-05-192-88/+57
| | | | | | No changes to the isel table size so the separation wasn't buying us anything. llvm-svn: 270026
* [X86] Simplify some type constraints by removing parts that were already ↵Craig Topper2016-05-191-12/+5
| | | | | | implied. llvm-svn: 270025
* CodeGen: Make the global-merge pass independently testable, and add a test.Peter Collingbourne2016-05-191-7/+20
| | | | llvm-svn: 270023
* Retry^3 "[ProfileData] (llvm) Use Error in InstrProf and Coverage, NFC"Vedant Kumar2016-05-197-327/+353
| | | | | | | | | | | | | | | Transition InstrProf and Coverage over to the stricter Error/Expected interface. Changes since the initial commit: - Fix error message printing in llvm-profdata. - Check errors in loadTestingFormat() + annotateAllFunctions(). - Defer error handling in InstrProfIterator to InstrProfReader. - Remove the base ProfError class to work around an MSVC ICE. Differential Revision: http://reviews.llvm.org/D19901 llvm-svn: 270020
* [GuardWidening] Use getEquivalentICmp to fold constant comparesSanjoy Das2016-05-191-13/+23
| | | | | | | `ConstantRange::getEquivalentICmp` is more general, and better factored. llvm-svn: 270019
* [ConstantRange] Add an getEquivalentICmp helperSanjoy Das2016-05-191-0/+26
| | | | | | | Currently only its unit test uses it, but this will be used in a later change to simplify some logic in the GuardWidening pass. llvm-svn: 270018
* [WebAssembly] Update WebAssembly target for r269988.Dan Gohman2016-05-192-4/+11
| | | | llvm-svn: 270017
* [X86] Remove some type constraint classes and use already existing stricter ↵Craig Topper2016-05-191-16/+10
| | | | | | classes. llvm-svn: 270013
* [AVX512] Strengthen type constraints for VFIXUPIMM patterns and combine the ↵Craig Topper2016-05-191-7/+8
| | | | | | type constraints for vector and scalar. llvm-svn: 270012
* reduce indentation; NFCISanjay Patel2016-05-191-9/+7
| | | | llvm-svn: 270007
* [AArch64] Push comment into function. NFC.Chad Rosier2016-05-181-9/+9
| | | | llvm-svn: 270003
* AMDGPU: Fix verifier error when spilling undef subregMatt Arsenault2016-05-181-3/+11
| | | | llvm-svn: 270002
* AMDGPU: Fix promote alloca for pointer loadsMatt Arsenault2016-05-181-3/+7
| | | | | | | If the load has a pointer type, we don't want to change its type. llvm-svn: 270000
* [LowerGuards] Rename variable; NFCSanjoy Das2016-05-181-3/+3
| | | | | | | PredicatePassProbability is a better name for what LikelyBranchWeight was trying to express. llvm-svn: 269999
* New pass: guard wideningSanjoy Das2016-05-185-0/+432
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Implement guard widening in LLVM. Description from GuardWidening.cpp: The semantics of the `@llvm.experimental.guard` intrinsic lets LLVM transform it so that it fails more often that it did before the transform. This optimization is called "widening" and can be used hoist and common runtime checks in situations like these: ``` %cmp0 = 7 u< Length call @llvm.experimental.guard(i1 %cmp0) [ "deopt"(...) ] call @unknown_side_effects() %cmp1 = 9 u< Length call @llvm.experimental.guard(i1 %cmp1) [ "deopt"(...) ] ... ``` to ``` %cmp0 = 9 u< Length call @llvm.experimental.guard(i1 %cmp0) [ "deopt"(...) ] call @unknown_side_effects() ... ``` If `%cmp0` is false, `@llvm.experimental.guard` will "deoptimize" back to a generic implementation of the same function, which will have the correct semantics from that point onward. It is always _legal_ to deoptimize (so replacing `%cmp0` with false is "correct"), though it may not always be profitable to do so. NB! This pass is a work in progress. It hasn't been tuned to be "production ready" yet. It is known to have quadriatic running time and will not scale to large numbers of guards Reviewers: reames, atrick, bogner, apilipenko, nlewycky Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20143 llvm-svn: 269997
* Follow-up patch of http://reviews.llvm.org/D19948 to handle missing profiles ↵Dehao Chen2016-05-181-18/+32
| | | | | | | | | | | | | | when simplifying CFG. Summary: Set default branch weight to 1:1 if one of the branch has profile missing when simplifying CFG. Reviewers: spatel, davidxl Subscribers: danielcdh, llvm-commits Differential Revision: http://reviews.llvm.org/D20307 llvm-svn: 269995
* [MBP] Remove a redundant skipFunction(). NFC.Haicheng Wu2016-05-181-3/+0
| | | | | | | | skipFunction() is called twice. Differential Revision: http://reviews.llvm.org/D20377 llvm-svn: 269994
* Work around a glibc bug: backtrace() spuriously fails ifRichard Smith2016-05-181-4/+51
| | | | | | | | | | | | - glibc is dynamically linked, and - libgcc_s is unavailable (for instance, another library is being used to provide the compiler runtime or libgcc is statically linked), and - the target is x86_64. If we run backtrace() and it fails to find any stack frames, try using _Unwind_Backtrace instead if available. llvm-svn: 269992
* fix formatting; NFCSanjay Patel2016-05-181-6/+3
| | | | llvm-svn: 269990
* Delete Reloc::Default.Rafael Espindola2016-05-1839-185/+273
| | | | | | | | | | | | Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. llvm-svn: 269988
* [lanai] Change the way flag setting instructions are checked.Jacques Pienaar2016-05-181-51/+11
| | | | | | | | isReturn() was returning different values with and without -g which led to different code being generated. Change isFlagSettingInstruction to query an instruction's effect on SR instead. llvm-svn: 269986
* [LoopUnrollAnalyzer] Take into account cost of instructions controlling ↵Michael Zolotukhin2016-05-181-0/+1
| | | | | | | | | branches, along with their operands. Previously, we didn't add their and their operands cost, which could've resulted in unrolling loops for no actual benefit. llvm-svn: 269985
* [WebAssembly] Disable the MachineScheduler.Dan Gohman2016-05-182-1/+14
| | | | llvm-svn: 269976
* clang-format SimplifyCFG.cpp.Dehao Chen2016-05-181-581/+625
| | | | llvm-svn: 269974
* AMDGPU: Fix incorrect simm checkJan Vesely2016-05-181-1/+1
| | | | | | | | | Use signed division otherwise all back jumps fail the check Fixes regression introduced in r269951 Differential Revision: http://reviews.llvm.org/D20380 llvm-svn: 269972
* When looking for a spill slot in reg scavenger, find one that matches RCKrzysztof Parzyszek2016-05-181-7/+38
| | | | | | | | | | | | When looking for an available spill slot, the register scavenger would stop after finding the first one with no register assigned to it. That slot may have size and alignment that do not meet the requirements of the register that is to be spilled. Instead, find an available slot that is the closest in size and alignment to one that is needed to spill a register from RC. Differential Revision: http://reviews.llvm.org/D20295 llvm-svn: 269969
* [AArch64] Minor refactoring. NFC.Chad Rosier2016-05-181-4/+5
| | | | llvm-svn: 269963
* clean up; NFCISanjay Patel2016-05-181-5/+4
| | | | llvm-svn: 269962
* pdbdump: Print out section offsets in the publics stream.Rui Ueyama2016-05-181-2/+6
| | | | llvm-svn: 269955
* Re-apply: [obj2yaml] [yaml2obj] Support MachO section and section_64Chris Bieneman2016-05-181-4/+27
| | | | | | This re-applies r269845, r269846, and r269850 with an included fix for a crash reported by zturner. llvm-svn: 269953
* AMDGPU: Error if branch distance exceeds limitMatt Arsenault2016-05-181-1/+5
| | | | llvm-svn: 269951
* AMDGPU: Other sizes of popcnt are fastMatt Arsenault2016-05-181-1/+1
| | | | | | | We can chain bcnt instructions together, so any width popcnt is pretty fast. llvm-svn: 269950
* Re-commit r269828 "X86: Avoid using _chkstk when lowering WIN_ALLOCA ↵Hans Wennborg2016-05-1810-38/+337
| | | | | | | | | | | | instructions" with an additional fix to make RegAllocFast ignore undef physreg uses. It would previously get confused about the "push %eax" instruction's use of eax. That method for adjusting the stack pointer is used in X86FrameLowering::emitSPUpdate as well, but since that runs after register-allocation, we didn't run into the RegAllocFast issue before. llvm-svn: 269949
* AMDGPU: Fix assert when erroring on a callMatt Arsenault2016-05-181-1/+5
| | | | | | | For some reason an assert is now hit when a valid chain is not returned, so return the entry chain. llvm-svn: 269948
* Trivial cleanups.Rafael Espindola2016-05-1811-22/+22
| | | | | | | This just clang formats and cleans comments in an area I am about to post a patch for review. llvm-svn: 269946
* AMDGPU: Handle alloca promoting with null operandsMatt Arsenault2016-05-181-2/+37
| | | | | | | If the second pointer in a multi-pointer instruction is a constant, we can replace the type. llvm-svn: 269945
* AMDGPU: Don't run passes that aren't usefulMatt Arsenault2016-05-181-0/+5
| | | | llvm-svn: 269943
* AMDGPU: Fix assert on ttmp registersMatt Arsenault2016-05-181-2/+2
| | | | | | | | | | | Use register class that does not include them when looking for unallocated registers. This is hit by the udiv v8i64 test in the opencl integer conformance test, and takes a few seconds to compile in a debug build so no test included. llvm-svn: 269938
* [PM] Port per-function SCCP to the new pass manager.Davide Italiano2016-05-184-45/+55
| | | | llvm-svn: 269937
* [Hexagon] Recognize "q" and "v" in inline-asm as register constraintsKrzysztof Parzyszek2016-05-182-2/+16
| | | | llvm-svn: 269933
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