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* Replace some explicit compare loops with std::equal.Benjamin Kramer2012-07-192-11/+2
| | | | | | No functionality change. llvm-svn: 160501
* [arm-fast-isel] Add support for vararg function calls.Jush Lu2012-07-191-28/+36
| | | | llvm-svn: 160500
* DebugInfo library: add support for fetching absolute paths to source filesAlexey Samsonov2012-07-194-7/+39
| | | | | | | | (instead of basenames) from DWARF. Use this behavior in llvm-dwarfdump tool. Reviewed by Benjamin Kramer. llvm-svn: 160496
* Fixed few warnings.Galina Kistanova2012-07-191-1/+1
| | | | llvm-svn: 160493
* Remove tabs.Bill Wendling2012-07-191-85/+85
| | | | llvm-svn: 160483
* Remove tabs.Bill Wendling2012-07-193-8/+8
| | | | llvm-svn: 160479
* Remove tabs.Bill Wendling2012-07-1917-79/+79
| | | | llvm-svn: 160477
* Remove tabs.Bill Wendling2012-07-193-13/+13
| | | | llvm-svn: 160476
* Remove tabs.Bill Wendling2012-07-1910-32/+35
| | | | llvm-svn: 160475
* X86: remove redundant cmp against zero.Manman Ren2012-07-182-15/+84
| | | | | | | | | Updated OptimizeCompare in peephole to remove redundant cmp against zero. We only remove Compare if CF and OF are not used. rdar://11855129 llvm-svn: 160454
* This patch fixes 8 out of 20 unexpected failures in "make check"Preston Gurd2012-07-182-1/+5
| | | | | | | | | | | | | | | when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! llvm-svn: 160451
* Adding some debug information to PassManagerVictor Oliveira2012-07-181-0/+20
| | | | llvm-svn: 160446
* Whitespace.Chad Rosier2012-07-181-18/+14
| | | | llvm-svn: 160445
* Fix a somewhat nasty crasher in PR13378. This crashes inside ofChandler Carruth2012-07-181-22/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LiveIntervals due to the two-addr pass generating bogus MI code. The crux of the issue was a loop nesting problem. The intent of the code which attempts to transform instructions before converting them to two-addr form is to defer and reprocess any transformed instructions as the second processing is likely to have more opportunities to coalesce copies, etc. Unfortunately, there was one section of processing that was not deferred -- the INSERT_SUBREG rewriting. Due to quirks of how this rewriting proceeded, not only did it occur early, it removed the bits of information needed for the deferred processing to correctly generate the necessary two address form (specifically inserting a copy), but didn't trigger any immediate assertions and produced what appeared to be already valid two-address from code. Thus, the assertion only fired much later in the pipeline. The fix is to hoist the transformation logic up layer to where it can more firmly defer all further processing, and to teach the normal processing to handle an edge case previously handled as part of the transformation logic. This edge case (already matched tied register operands) needs to *not* defer any steps. As has been brought up repeatedly in the process: wow does this code need refactoring. I *may* squeeze in some time to at least bring sanity to this loop... but wow... =] Thanks to Jakob for helpful hints on the way here, and the review. llvm-svn: 160443
* Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.Andrew Trick2012-07-181-4/+11
| | | | | | Based on Evan's suggestion without a commitable test. llvm-svn: 160441
* whitespaceAndrew Trick2012-07-181-2/+2
| | | | llvm-svn: 160440
* The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem2012-07-181-6/+8
| | | | | | | | | | | | load source operand is used by multiple nodes. The v2i64 broadcast was emulated by shuffling the two lower i32 elements to the upper two. We had a bug in the immediate used for the broadcast. Replacing 0 to 0x44. 0x44 means [01|00|01|00] which corresponds to the correct lane. Patch by Michael Kuperstein. llvm-svn: 160430
* Mips specific inline asm operand modifier 'M':Jack Carter2012-07-181-3/+8
| | | | | | | | | | | | | | | | | | | | | | Print the high order register of a double word register operand. In 32 bit mode, a 64 bit double word integer will be represented by 2 32 bit registers. This modifier causes the high order register to be used in the asm expression. It is useful if you are using doubles in assembler and continue to control register to variable relationships. This patch also fixes a related bug in a previous patch: case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand case 'M': // High order register of a double word register operand I got 'D' and 'M' confused. The second part of a double word operand will only match 'M' for one of the endianesses. I had 'L' and 'D' be the opposite twins when 'L' and 'M' are. llvm-svn: 160429
* Remove tab characters.Craig Topper2012-07-181-13/+13
| | | | llvm-svn: 160425
* Fix typo in error message and remove some tab characters.Craig Topper2012-07-181-5/+5
| | | | llvm-svn: 160423
* indvars: drive by heuristics fix.Andrew Trick2012-07-181-1/+1
| | | | | | Minor oversight noticed by inspection. Sorry no unit test. llvm-svn: 160422
* indvars: Linear function test replace should avoid reusing undef.Andrew Trick2012-07-181-5/+67
| | | | | | | | | | | | | | | | | | | | | | | Fixes PR13371: indvars pass incorrectly substitutes 'undef' values. I do not like this fix. It's needed until/unless the meaning of undef changes. It attempts to be complete according to the IR spec, but I don't have much confidence in the implementation given the difficulty testing undefined behavior. Worse, this invalidates some of my hard-fought work on indvars and LSR to optimize pointer induction variables. It results benchmark regressions, which I'll track internally. On x86_64 no LTO I see: -3% huffbench -3% 400.perlbench -8% fhourstones My only suggestion for recovering is to change the meaning of undef. If we could trust an arbitrary instruction to produce a some real value that can be manipulated (e.g. incremented) according to non-undef rules, then this case could be easily handled with SCEV. llvm-svn: 160421
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-183-15/+66
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* Fixed few warnings.Galina Kistanova2012-07-181-1/+2
| | | | llvm-svn: 160419
* ignore 'invoke @llvm.donothing', but still keep the edge to the continuation BBNuno Lopes2012-07-181-1/+1
| | | | llvm-svn: 160411
* More replacing of target-dependent intrinsics with target-indepdent Joel Jones2012-07-182-3/+13
| | | | | | | | | | | | | | | | | | | | | intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> llvm-svn: 160410
* Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.Akira Hatanaka2012-07-172-93/+117
| | | | | | Patch by Reed Kotler. llvm-svn: 160403
* Back out r160101 and instead implement a dag combine to recover from ↵Evan Cheng2012-07-173-7/+29
| | | | | | instcombine transformation. llvm-svn: 160387
* Add some trace output to TwoAddressInstructionPass.Jakob Stoklund Olesen2012-07-171-1/+4
| | | | llvm-svn: 160380
* Remove unused variable.Benjamin Kramer2012-07-171-1/+0
| | | | llvm-svn: 160372
* simplify getSetSize() per Duncan's commentsNuno Lopes2012-07-171-6/+5
| | | | llvm-svn: 160368
* Improve behavior of DebugInfoEntryMinimal::getSubprogramName() introduced in ↵Alexey Samsonov2012-07-173-28/+35
| | | | | | | | | | | r159512. To fetch a subprogram name we should not only inspect the DIE for this subprogram, but optionally inspect its specification, or its abstract origin (even if there is no inlining), or even specification of an abstract origin. Reviewed by Benjamin Kramer. llvm-svn: 160365
* [asan] more code to merge crash callbacks. Doesn't fully work yet, but ↵Kostya Serebryany2012-07-171-12/+58
| | | | | | allows to hold performance experiments llvm-svn: 160361
* Fix a crash in the legalization of large vectors.Nadav Rotem2012-07-171-6/+3
| | | | | | | When truncating a result of a vector that is split we need to use the result of the split vector, and not re-split the dead node. llvm-svn: 160357
* Implement r160312 as target indepedenet dag combine.Evan Cheng2012-07-172-44/+27
| | | | llvm-svn: 160354
* Make sure constant bitwidth is <= 64 bit before calling getSExtValue().Evan Cheng2012-07-171-1/+2
| | | | llvm-svn: 160350
* This is another case where instcombine demanded bits optimization createdEvan Cheng2012-07-173-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
* Reapply r160340. LSR: Limit CollectSubexprs.Andrew Trick2012-07-171-28/+52
| | | | | | Speculatively fix crashes by code inspection. Can't reproduce them yet. llvm-svn: 160344
* Revert "LSR: try not to blow up solving combinatorial problems brute force."Andrew Trick2012-07-171-51/+28
| | | | | | Some units tests crashed on a different platform. llvm-svn: 160341
* LSR: try not to blow up solving combinatorial problems brute force.Andrew Trick2012-07-171-28/+51
| | | | | | | | | | This places limits on CollectSubexprs to constrains the number of reassociation possibilities. It limits the recursion depth and skips over chains of nested recurrences outside the current loop. Fixes PR13361. Although underlying SCEV behavior is still potentially bad. llvm-svn: 160340
* fix PR13339 (remove the predecessor from the unwind BB when removing an invoke)Nuno Lopes2012-07-161-0/+1
| | | | llvm-svn: 160325
* teach ConstantRange that zero times X is always zeroNuno Lopes2012-07-161-0/+6
| | | | llvm-svn: 160317
* For something likeEvan Cheng2012-07-161-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | uint32_t hi(uint64_t res) { uint_32t hi = res >> 32; return !hi; } llvm IR looks like this: define i32 @hi(i64 %res) nounwind uwtable ssp { entry: %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext } The optimizer has optimize away the right shift and truncate but the resulting constant is too large to fit in the 32-bit immediate field. The resulting x86 code is worse as a result: movabsq $4294967296, %rax ## imm = 0x100000000 cmpq %rax, %rdi sbbl %eax, %eax andl $1, %eax This patch teaches the x86 lowering code to handle ult against a large immediate with trailing zeros. It will issue a right shift and a truncate followed by a comparison against a shifted immediate. shrq $32, %rdi testl %edi, %edi sete %al movzbl %al, %eax It also handles a ugt comparison against a large immediate with trailing bits set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1 rdar://11866926 llvm-svn: 160312
* Minor cleanup and docs.Nadav Rotem2012-07-161-1/+3
| | | | llvm-svn: 160311
* Make ComputeDemandedBits return a deterministic result when computing an ↵Nadav Rotem2012-07-161-0/+1
| | | | | | | | | | | AssertZext value. In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits reported that some of the bits were both known to be one and known to be zero. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160305
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-16114-28329/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
* Revert "Build script changes for R600/SI Codegen v6"Tom Stellard2012-07-161-1/+1
| | | | | | This reverts commit e3013202259ed1e006c21817c63cf25d75982721. llvm-svn: 160301
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, ↵Tom Stellard2012-07-161-2/+2
| | | | | | | | <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>" This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590. llvm-svn: 160299
* Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵Tom Stellard2012-07-162-3/+1
| | | | | | | | AMDGPUCommonTableGen." This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2. llvm-svn: 160298
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as ↵Tom Stellard2012-07-161-8/+8
| | | | | | | | conditional operator..." This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a. llvm-svn: 160297
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