Implement r160312 as target indepedenet dag combine.

llvm-svn: 160354

2 files changed, 27 insertions, 44 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index d439a6f8699..14f0ef518fe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2342,6 +2342,33 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
             return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
           }
         }
+      } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
+                 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
+        bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
+        // X <  0x100000000 -> (X >> 32) <  1
+        // X >= 0x100000000 -> (X >> 32) >= 1
+        // X <= 0x0ffffffff -> (X >> 32) <  1
+        // X >  0x0ffffffff -> (X >> 32) >= 1
+        unsigned ShiftBits;
+        APInt NewC = C1;
+        ISD::CondCode NewCond = Cond;
+        if (AdjOne) {
+          ShiftBits = C1.countTrailingOnes();
+          NewC = NewC + 1;
+          NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
+        } else {
+          ShiftBits = C1.countTrailingZeros();
+        }
+        NewC = NewC.lshr(ShiftBits);
+        if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
+          EVT ShiftTy = DCI.isBeforeLegalize() ?
+            getPointerTy() : getShiftAmountTy(N0.getValueType());
+          EVT CmpTy = N0.getValueType();
+          SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
+                                      DAG.getConstant(ShiftBits, ShiftTy));
+          SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
+          return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
+        }
       }
     }
   }
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 347f1977e71..4f642ec542a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3059,50 +3059,6 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
         RHS = DAG.getConstant(0, RHS.getValueType());
         return X86::COND_LE;
       }
-      if (SetCCOpcode == ISD::SETULT || SetCCOpcode == ISD::SETUGE) {
-        unsigned TrailZeros = RHSC->getAPIntValue().countTrailingZeros();
-        if (TrailZeros >= 32) {
-          // The constant doesn't fit in cmp immediate field. Right shift LHS by
-          // the # of trailing zeros and truncate it to 32-bit. Then compare
-          // against shifted RHS.
-          assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
-          DebugLoc dl = LHS.getDebugLoc();
-          LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
-                            DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
-                                        DAG.getConstant(TrailZeros, MVT::i8)));
-          uint64_t C = RHSC->getZExtValue() >> TrailZeros;
-
-          if (SetCCOpcode == ISD::SETULT) {
-            // X < 0x300000000 -> (X >> 32) < 3
-            // X < 0x100000000 -> (X >> 32) == 0
-            // X < 0x200000000 -> (X >> 33) == 0
-            if (C == 1) {
-              RHS = DAG.getConstant(0, MVT::i32);
-              return X86::COND_E;
-            }
-            RHS = DAG.getConstant(C, MVT::i32);
-            return X86::COND_B;
-          } else /* SetCCOpcode == ISD::SETUGE */ {
-            // X >= 0x100000000 -> (X >> 32) >= 1
-            RHS = DAG.getConstant(C, MVT::i32);
-            return X86::COND_AE;
-          }
-        }
-      }
-      if (SetCCOpcode == ISD::SETUGT) {
-        unsigned TrailOnes = RHSC->getAPIntValue().countTrailingOnes();
-        if (TrailOnes >= 32 && !RHSC->isAllOnesValue()) {
-          assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
-          DebugLoc dl = LHS.getDebugLoc();
-          LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
-                            DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
-                                        DAG.getConstant(TrailOnes, MVT::i8)));
-          uint64_t C = (RHSC->getZExtValue()+1) >> TrailOnes;
-          // X >  0x0ffffffff -> (X >> 32) >= 1
-          RHS = DAG.getConstant(C, MVT::i32);
-          return X86::COND_AE;
-        }
-      }
     }
 
     switch (SetCCOpcode) {