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* Fix covered-switch-default warningSimon Pilgrim2016-09-181-5/+4
| | | | llvm-svn: 281865
* [X86] Fix typo in comment. NFCCraig Topper2016-09-181-1/+1
| | | | llvm-svn: 281862
* [AVX-512] Add memory load patterns for the legacy SSE scalar fp to integer ↵Craig Topper2016-09-181-1/+16
| | | | | | conversion intrinsics to be consistent across all intruction sets. llvm-svn: 281861
* [AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the ↵Craig Topper2016-09-181-8/+8
| | | | | | correct register class. llvm-svn: 281860
* Fix built bot failureXinliang David Li2016-09-181-1/+1
| | | | llvm-svn: 281859
* [Profile] Implement select instruction instrumentation in IR PGOXinliang David Li2016-09-182-11/+151
| | | | | | Differential Revision: http://reviews.llvm.org/D23727 llvm-svn: 281858
* [Loop Vectorizer] Consecutive memory access - fixed and simplifiedElena Demikhovsky2016-09-182-85/+9
| | | | | | | | | Amended consecutive memory access detection in Loop Vectorizer. Load/Store were not handled properly without preceding GEP instruction. Differential Revision: https://reviews.llvm.org/D20789 llvm-svn: 281853
* [X86][SSE] Improve recognition of uitofp conversions that can be performed ↵Simon Pilgrim2016-09-182-7/+9
| | | | | | | | | | | | | | as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
* [Loop vectorizer] Simplified GEP cloning. NFC.Elena Demikhovsky2016-09-181-35/+26
| | | | | | | | | Simplified GEP cloning in vectorizeMemoryInstruction(). Added an assertion that checks consecutive GEP, which should have only one loop-variant operand. Differential Revision: https://reviews.llvm.org/D24557 llvm-svn: 281851
* Change the order of the splitted store from high - low to low - high.Wei Mi2016-09-181-2/+2
| | | | | | | It is a trivial change which could make the testcase easier to be reused for the store splitting in CodeGenPrepare. llvm-svn: 281846
* [libFuzzer] use 'if guard' instead of 'if guard >= 0' with trace-pc; change ↵Kostya Serebryany2016-09-183-47/+47
| | | | | | the guard type to intptr_t; use separate array for 8-bit counters llvm-svn: 281845
* [lib/LTO] Try harder to reduce code duplication. NFCI.Davide Italiano2016-09-171-13/+14
| | | | llvm-svn: 281843
* [ThinLTO] Ensure anonymous globals renamed even at -O0Teresa Johnson2016-09-171-1/+9
| | | | | | | | | | | | | | | | | | | | | | Summary: This fixes an issue when files are compiled with -flto=thin at default -O0. We need to rename anonymous globals before attempting to write the module summary because all values need names for the summary. This was happening at -O1 and above, but not before the early exit when constructing the pipeline for -O0. Also add an internal -prepare-for-thinlto option to enable this to be tested via opt. Fixes PR30419. Reviewers: mehdi_amini Subscribers: probinson, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24701 llvm-svn: 281840
* [X86][SSE] Improve target shuffle mask extractionSimon Pilgrim2016-09-171-10/+14
| | | | | | Add ability to extract vXi64 'vzext_movl' masks on 32-bit targets llvm-svn: 281834
* [Hexagon] segv while processing SUnit with nullNodePtrRon Lieberman2016-09-171-0/+4
| | | | | | Added BoundaryNode check to isBestZeroLatency function. llvm-svn: 281825
* AMDGPU: Fix broken FrameIndex handlingMatt Arsenault2016-09-175-99/+19
| | | | | | | | | | | | | | | | | We were trying to avoid using a FrameIndex operand in non-pointer operands in a convoluted way, and would break because of using TargetFrameIndex. The TargetFrameIndex should only be used in the case where it makes sense to fold it as part of the addressing mode, otherwise it requires materialization like a normal constant. This wasn't working reliably and failed in the added testcase, hitting the assert when processing the frame index. The TargetFrameIndex was coming from trying to produce an AssertZext limiting the maximum stack size. I'm not sure this was correct to begin with, because it is apparently possible to have a single workitem dispatch that requires all 4G of private memory. llvm-svn: 281824
* AMDGPU: Rename spill operands to match real instructionMatt Arsenault2016-09-172-13/+13
| | | | llvm-svn: 281823
* AMDGPU: Push bitcasts through build_vectorMatt Arsenault2016-09-171-0/+27
| | | | | | | | This reduces the number of copies and reg_sequences when using fp constant vectors. This significantly reduces the code size in local-stack-alloc-bug.ll llvm-svn: 281822
* [libFuzzer] properly reset the guards when reseting the coverage. Also try ↵Kostya Serebryany2016-09-173-1/+12
| | | | | | to fix check-fuzzer on the bot llvm-svn: 281814
* Don't create a SymbolTable in Function when the LLVMContext discards value ↵Mehdi Amini2016-09-178-15/+19
| | | | | | | | | | | | | | names (NFC) The ValueSymbolTable is used to detect name conflict and rename instructions automatically. This is not needed when the value names are automatically discarded by the LLVMContext. No functional change intended, just saving a little bit of memory. This is a recommit of r281806 after fixing the accessor to return a pointer instead of a reference and updating all the call-sites. llvm-svn: 281813
* [MIR Parser] Fix Build!Mehdi Amini2016-09-171-1/+1
| | | | | | Last-second refactoring before push was bad idea... llvm-svn: 281812
* MIR Parser: issue an error when the Context discard value names.Mehdi Amini2016-09-171-0/+8
| | | | | | This is in line with the LLParser behavior llvm-svn: 281811
* [libFuzzer] change trace-pc to use 8-byte guardsKostya Serebryany2016-09-1710-32/+156
| | | | llvm-svn: 281810
* [sanitizer-coverage] change trace-pc to use 8-byte guardsKostya Serebryany2016-09-171-24/+27
| | | | llvm-svn: 281809
* Revert "Don't create a SymbolTable in Function when the LLVMContext discards ↵Mehdi Amini2016-09-171-4/+2
| | | | | | | | | value names (NFC)" This reverts commit r281806. It introduces undefined behavior as an API is returning a reference to the Symtab llvm-svn: 281808
* Don't create a SymbolTable in Function when the LLVMContext discards value ↵Mehdi Amini2016-09-171-2/+4
| | | | | | | | | | | names (NFC) The ValueSymbolTable is used to detect name conflict and rename instructions automatically. This is not needed when the value names are automatically discarded by the LLVMContext. No functional change intended, just saving a little bit of memory. llvm-svn: 281806
* AMDGPU: Use i64 scalar compare instructionsMatt Arsenault2016-09-174-12/+45
| | | | | | VI added eq/ne for i64, so use them. llvm-svn: 281800
* AMDGPU/SI: Fix kernel argument ABI for HSATom Stellard2016-09-161-1/+2
| | | | | | | | | | | | Summary: i8, i16, and f16 values are not extended to 32-bit in the HSA kernel ABI. Reviewers: arsenm Subscribers: arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D24621 llvm-svn: 281789
* [InstCombine] canonicalize vector select with constant vector condition to ↵Sanjay Patel2016-09-161-0/+39
| | | | | | | | | | | | | | | | | | | | shuffle As discussed on llvm-dev ( http://lists.llvm.org/pipermail/llvm-dev/2016-August/104210.html ): turn a vector select with constant condition operand into a shuffle as a canonicalization step. Shuffles may be easier to reason about in conjunction with other shuffles and insert/extract. Possible known (minor?) regressions from this change are filed as: https://llvm.org/bugs/show_bug.cgi?id=28530 https://llvm.org/bugs/show_bug.cgi?id=28531 https://llvm.org/bugs/show_bug.cgi?id=30371 If something terrible happens to perf after this commit, feel free to revert until a backend fix is in place. Differential Revision: https://reviews.llvm.org/D24279 llvm-svn: 281787
* AMDGPU: Allow some control flow intrinsics to be CSEdMatt Arsenault2016-09-165-27/+80
| | | | | | | | | | | These clean up some unnecessary or instructions in cases with complex loops. In the original testcase I noticed this, the same or with exec was repeated 5 or 6 times in a row. With this only one is emitted or sometimes a copy. llvm-svn: 281786
* [safestack] Fix assertion failure in stack coloring.Evgeniy Stepanov2016-09-161-4/+6
| | | | | | | | | | This is a fix for PR30318. Clang may generate IR where an alloca is already live when entering a BB with lifetime.start. In this case, conservatively extend the alloca lifetime all the way back to the block entry. llvm-svn: 281784
* [RegAllocGreedy] Fix the list of NewVRegs for last chance recoloring.Quentin Colombet2016-09-161-2/+22
| | | | | | | | | | | | | | | | | When trying to recolor a register we may split live-ranges in the process. When we create new live-ranges we will have to process them, but when we move a register from Assign to Split, the allocation is not changed until the whole recoloring session is successful. Therefore, only push the live-ranges that changed from Assign to Split when the recoloring is successful. Same as the previous commit, I was not able to produce a test case that reproduce the problem with in-tree targets. Note: The bug has been here since the recoloring scheme has been added back in r200883 (Feb 2014). llvm-svn: 281783
* [RegAllocGreedy] Fix an assertion and condition when last chance recoloring ↵Quentin Colombet2016-09-161-2/+3
| | | | | | | | | | | | | | | | is used. When last chance recoloring is used, the list of NewVRegs may not be empty when calling selectOrSplitImpl. Indeed, another coloring may have taken place with splitting/spilling in the same recoloring session. Relax an assertion to take this into account and adapt a condition to act as if the NewVRegs were local to this selectOrSplitImpl instance. Unfortunately I am unable to produce a test case for this, I was only able to reproduce the conditions on an out-of-tree target. llvm-svn: 281782
* AMDGPU: Refactor kernel argument loweringTom Stellard2016-09-164-52/+109
| | | | | | | | | | | | | | | | | | | Summary: The main challenge in lowering kernel arguments for AMDGPU is determing the memory type of the argument. The generic calling convention code assumes that only legal register types can be stored in memory, but this is not the case for AMDGPU. This consolidates all the logic AMDGPU uses for deducing memory types into a single function. This will make it much easier to support different ABIs in the future. Reviewers: arsenm Subscribers: arsenm, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D24614 llvm-svn: 281781
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-167-51/+152
| | | | llvm-svn: 281780
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-167-13/+22
| | | | | | | | | | | | | | Summary: mesa3d will use the same kernel calling convention as amdhsa, but it will handle everything else like the default 'unknown' OS type. Reviewers: arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22783 llvm-svn: 281779
* [InstCombine] allow vector types for constant folding / computeKnownBits ↵Sanjay Patel2016-09-162-6/+8
| | | | | | | | | | | | | | | | (PR24942) computeKnownBits() already works for integer vectors, so allow vector types when calling that from InstCombine. I don't think the change to use m_APInt in computeKnownBits is strictly necessary because we do check for ConstantVector later, but it's more efficient to handle the splat case without needing to loop on vector elements. This should work with InstSimplify, but doesn't yet, so I made that a FIXME comment on the test for PR24942: https://llvm.org/bugs/show_bug.cgi?id=24942 Differential Revision: https://reviews.llvm.org/D24677 llvm-svn: 281777
* [LTO] Add ability to parse AA pipelines.Davide Italiano2016-09-161-1/+10
| | | | | | | This is supposed to be a drop in replacement for what lld provides via --lto-newpm-aa-pipeline. llvm-svn: 281774
* Defer asm errors to post-statement failureNirav Dave2016-09-1610-352/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing AsmParser initialization and X86 inline asm error cleanup. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281762
* Change extractProfMetadata and extractProfTotalWeight to const member function.Dehao Chen2016-09-161-26/+18
| | | | llvm-svn: 281760
* LoopDistribute should preserve GlobalsAA.Eli Friedman2016-09-161-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D24204 llvm-svn: 281758
* LoopLoadElimination should preserve GlobalsAA.Eli Friedman2016-09-161-0/+2
| | | | | | | | Avoids losing GlobalsAA in the standard pass pipeline. Differential Revision: https://reviews.llvm.org/D24094 llvm-svn: 281757
* Fix test after renaming -name-anon-functions pass to -name-anon-globalsMehdi Amini2016-09-161-1/+1
| | | | llvm-svn: 281752
* Actually remove the Mangler from the AsmPrinter and clean up the places it ↵Eric Christopher2016-09-167-15/+7
| | | | | | was "used" but not used. llvm-svn: 281749
* Fix a hidden use of grabbing the Mangler from the AsmPrinter and updateEric Christopher2016-09-161-4/+4
| | | | | | accordingly. llvm-svn: 281748
* Rename NameAnonFunctions to NameAnonGlobals to match what it is doing (NFC)Mehdi Amini2016-09-166-30/+30
| | | | llvm-svn: 281745
* Fix NameAnonFunctions pass: for ThinLTO we need to rename global variables ↵Mehdi Amini2016-09-161-5/+10
| | | | | | | | | | | as well A follow-up patch will rename this pass and the source file accordingly, but I figured the non-NFC change will be easier to spot in isolation. Differential Revision: https://reviews.llvm.org/D24641 llvm-svn: 281744
* [InstCombine] add helper functions for visitICmpInst(); NFCISanjay Patel2016-09-162-523/+559
| | | | llvm-svn: 281743
* [IRObjectFile] Turn llvm_unreachable("foo") into something more explicative.Davide Italiano2016-09-161-1/+1
| | | | llvm-svn: 281742
* [LTO] Prevent asm references to be dropped from the output.Davide Italiano2016-09-161-0/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D24617 llvm-svn: 281741
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