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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-17 15:52:37 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-17 15:52:37 +0000 |
| commit | bcfd94c2982e6b8468596390234832653a56fb54 (patch) | |
| tree | f1807cc629fb640b6500b58bb7dab8951da4115e /llvm/lib | |
| parent | d99ef1144b38f41ca2e68bf666490110237ec2bf (diff) | |
| download | bcm5719-llvm-bcfd94c2982e6b8468596390234832653a56fb54.tar.gz bcm5719-llvm-bcfd94c2982e6b8468596390234832653a56fb54.zip | |
AMDGPU: Rename spill operands to match real instruction
llvm-svn: 281823
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 20 |
2 files changed, 13 insertions, 13 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index e201736cc2f..7daa1032f05 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1210,8 +1210,8 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { SchedRW = [WriteVMEM] in { def _SAVE : VPseudoInstSI < (outs), - (ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$scratch_rsrc, - SReg_32:$scratch_offset, i32imm:$offset)> { + (ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$srsrc, + SReg_32:$soffset, i32imm:$offset)> { let mayStore = 1; let mayLoad = 0; // (2 * 4) + (8 * num_subregs) bytes maximum @@ -1220,7 +1220,7 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { def _RESTORE : VPseudoInstSI < (outs vgpr_class:$vdata), - (ins i32imm:$vaddr, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset, + (ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset, i32imm:$offset)> { let mayStore = 0; let mayLoad = 1; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index bcee76f5299..4e842ee9870 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -488,9 +488,9 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, Size, Align); BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE)) .addReg(TmpReg, RegState::Kill) // src - .addFrameIndex(Index) // frame_idx - .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc - .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset + .addFrameIndex(Index) // vaddr + .addReg(MFI->getScratchRSrcReg()) // srrsrc + .addReg(MFI->getScratchWaveOffsetReg()) // soffset .addImm(i * 4) // offset .addMemOperand(MMO); } @@ -546,9 +546,9 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, PtrInfo, MachineMemOperand::MOLoad, Size, Align); BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg) - .addFrameIndex(Index) // frame_idx - .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc - .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset + .addFrameIndex(Index) // vaddr + .addReg(MFI->getScratchRSrcReg()) // srsrc + .addReg(MFI->getScratchWaveOffsetReg()) // soffset .addImm(i * 4) // offset .addMemOperand(MMO); BuildMI(*MBB, MI, DL, @@ -576,8 +576,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, case AMDGPU::SI_SPILL_V32_SAVE: buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET, TII->getNamedOperand(*MI, AMDGPU::OpName::vdata), - TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(), - TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(), + TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(), + TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(), FrameInfo.getObjectOffset(Index) + TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS); MI->eraseFromParent(); @@ -591,8 +591,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, case AMDGPU::SI_SPILL_V512_RESTORE: { buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET, TII->getNamedOperand(*MI, AMDGPU::OpName::vdata), - TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(), - TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(), + TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(), + TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(), FrameInfo.getObjectOffset(Index) + TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS); MI->eraseFromParent(); |
