summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Compress flags in X86 op folding to reduce space in static tables.Craig Topper2012-06-231-16/+16
| | | | llvm-svn: 159073
* Make helper method static since it doesn't use anything in the class.Craig Topper2012-06-231-3/+3
| | | | llvm-svn: 159071
* Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with ↵Craig Topper2012-06-232-26/+9
| | | | | | intrinsic patterns. Mem forms omitted because the load size is only 64-bits. llvm-svn: 159070
* Teach LiveVariables to handle <undef> operands.Jakob Stoklund Olesen2012-06-231-3/+5
| | | | | | | | It's simple: Don't treat <undef> operands as uses, and don't assume a virtual register has a defining instruction unless a real use has been seen. llvm-svn: 159061
* Handle aliases to tls variables in all architectures, not just x86.Rafael Espindola2012-06-232-8/+11
| | | | llvm-svn: 159058
* (sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng2012-06-233-7/+21
| | | | | | | | | | | | | | | There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
* BoundsChecking: attach debug info to traps to make my life a bit more saneNuno Lopes2012-06-231-9/+10
| | | | llvm-svn: 159055
* ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach2012-06-222-2/+13
| | | | | | | | | | | As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
* Add support for the PPC isel instruction.Hal Finkel2012-06-228-14/+84
| | | | | | | The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. llvm-svn: 159045
* Remove ProcessImplicitDefs.h which was unused.Jakob Stoklund Olesen2012-06-221-2/+27
| | | | | | The ProcessImplicitDefs class can be local to its implementation file. llvm-svn: 159041
* Also verify the def index for early clobbers.Jakob Stoklund Olesen2012-06-221-2/+3
| | | | llvm-svn: 159039
* Whitespace.Chad Rosier2012-06-221-8/+8
| | | | llvm-svn: 159035
* Delete a boring statistic.Jakob Stoklund Olesen2012-06-221-6/+0
| | | | llvm-svn: 159030
* Store live intervals in an IndexedMap.Jakob Stoklund Olesen2012-06-221-14/+8
| | | | | | It is both smaller and faster than DenseMap. llvm-svn: 159029
* Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel2012-06-224-10/+10
| | | | | | | | | | Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 159027
* EmitZerofill should take a 64-bit size or else it's chopping off large ↵Evan Cheng2012-06-226-10/+10
| | | | | | zero-filled global. rdar://11729134 llvm-svn: 159023
* Fix a crash in --debug code.Jakob Stoklund Olesen2012-06-221-2/+6
| | | | | | Don't try to print out the live range of a physreg. llvm-svn: 159021
* Don't depend on live ranges being present.Jakob Stoklund Olesen2012-06-221-3/+8
| | | | | | | DBG_VALUE instructions could be referring to non-existing virtual registers. llvm-svn: 159020
* Simplify handleMove() a bit.Jakob Stoklund Olesen2012-06-221-4/+4
| | | | | | | There is no need to check for physreg live ranges. They don't exist any more. llvm-svn: 159019
* Stop computing physreg live ranges.Jakob Stoklund Olesen2012-06-221-189/+1
| | | | | | Everyone is using on-demand regunit ranges now. llvm-svn: 159018
* Remove some redundant LIS->hasInterval() checks.Jakob Stoklund Olesen2012-06-221-22/+0
| | | | | | | These functions only operate on virtual registers now, and they all have live ranges. llvm-svn: 159015
* Use MRI::isConstantPhysReg() to check remat feasibility.Jakob Stoklund Olesen2012-06-221-4/+8
| | | | | | | Don't depend on LiveIntervals::hasInterval() to determine if a physreg is reserved and constant. llvm-svn: 159013
* Use regunit liveness to guide LiveDebugVariables.Jakob Stoklund Olesen2012-06-221-5/+18
| | | | | | This should produce the same results as using physreg liveness directly. llvm-svn: 159009
* Remove LiveIntervals::trackingRegUnits().Jakob Stoklund Olesen2012-06-223-71/+13
| | | | | | | | | With regunit liveness permanently enabled, this function would always return true. Also remove now obsolete code for checking physreg interference. llvm-svn: 159006
* Revert remaining part of r93200: "Disable folding sext(trunc(x)) -> x"Jakob Stoklund Olesen2012-06-221-9/+4
| | | | | | | | | | | This fixes PR5997. These transforms were disabled because codegen couldn't deal with other uses of trunc(x). This is now handled by the peephole pass. This causes no regressions on x86-64. llvm-svn: 159003
* simplify code from previous commits (Thanks Duncan)Nuno Lopes2012-06-221-7/+2
| | | | llvm-svn: 158999
* Fixed r158979.Stepan Dyatkovskiy2012-06-222-4/+19
| | | | | | | | | | Original message: Performance optimizations: - SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges. - Optimized IntItem, added APInt value caching. - Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only. llvm-svn: 158997
* Remove another duplicated variable. We only need one to tell us if the linkerRafael Espindola2012-06-223-3/+1
| | | | | | knows dwarf or not. llvm-svn: 158993
* Fix a FIXME: DwarfRequiresRelocationForSectionOffset is the same asRafael Espindola2012-06-224-5/+3
| | | | | | DwarfUsesRelocationsAcrossSections. llvm-svn: 158992
* Revert commit 158979 (dyatkovskiy) since it is causing several buildbots toDuncan Sands2012-06-221-11/+2
| | | | | | | | | | | | | fail. Original commit message: Performance optimizations: - SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges. - Optimized IntItem, added APInt value caching. - Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only. On my machine these optimizations gave about 4-6% of compile-time improvement. llvm-svn: 158986
* Performance optimizations:Stepan Dyatkovskiy2012-06-221-2/+11
| | | | | | | | | | - SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges. - Optimized IntItem, added APInt value caching. - Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only. On my machine these optimizations gave about 4-6% of compile-time improvement. llvm-svn: 158979
* Use "NoItineraries" for processors with no itineraries.Andrew Trick2012-06-224-9/+2
| | | | | | | | This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. llvm-svn: 158963
* Functions calling __builtin_eh_return must have a frame pointer.Jakob Stoklund Olesen2012-06-221-1/+1
| | | | | | | | | | | | | | The code in X86TargetLowering::LowerEH_RETURN() assumes that a frame pointer exists, but the frame pointer was forced by the presence of llvm.eh.unwind.init which isn't guaranteed. If llvm.eh.unwind.init is actually required in functions calling eh.return (is it?), we should diagnose that instead of emitting bad machine code. This should fix the dragonegg-x86_64-linux-gcc-4.6-test bot. llvm-svn: 158961
* ARM scheduling fix: don't guess at implicit operand latency.Andrew Trick2012-06-221-5/+9
| | | | | | | | | | This is a minor drive-by fix with no robust way to unit test. As an example see neon-div.ll: SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill> val SU(1): Latency=2 Reg=%Q8 ...should be latency=1 llvm-svn: 158960
* ARM scheduling fix: compute predicated implicit use properly.Andrew Trick2012-06-221-3/+1
| | | | | | | | Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. llvm-svn: 158959
* Emit relocations for DW_AT_location entries on systems which need it. This isNick Lewycky2012-06-224-13/+18
| | | | | | a recommit of r127757. Fixes PR9493. Patch by Paul Robinson! llvm-svn: 158957
* Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames2012-06-223-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. llvm-svn: 158956
* Convert the PPC backend to use the new FMA infrastructure.Hal Finkel2012-06-224-42/+48
| | | | | | | The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. llvm-svn: 158955
* fix whitespace in my last commit.Nuno Lopes2012-06-221-1/+1
| | | | | | sorry for the churn :S enough for today; going to sleep. llvm-svn: 158953
* remove extractMallocCallFromBitCast, since it was tailor maded for its sole ↵Nuno Lopes2012-06-222-10/+5
| | | | | | user. Update GlobalOpt accordingly. llvm-svn: 158952
* instcombine: disable optimization of 'invoke null/undef'. I'll move this ↵Nuno Lopes2012-06-211-11/+11
| | | | | | | | functionality to SimplifyCFG (since we cannot make changes to the CFG here). Fixes the crashes with the attached test case llvm-svn: 158951
* Look pass zext to strength reduce an udiv. Patch by David Majnemer. ↵Evan Cheng2012-06-211-1/+4
| | | | | | rdar://11721329 llvm-svn: 158946
* The inline asm operand modifier 'n' is suppose Jack Carter2012-06-211-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Negate the immediate constant Several Architectures such as x86 have local implementations of operand modifier 'n' which go beyond the above description slightly. This won't affect them. Affected files: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'n' to the switch cases. test/CodeGen/Generic/asm-large-immediate.ll Generic compiled test (x86 for me) test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter llvm-svn: 158939
* Add support for invoke to the MemoryBuiltin analysid.Nuno Lopes2012-06-213-17/+29
| | | | | | | | Update comments accordingly. Make instcombine remove useless invokes to C++'s 'new' allocation function (test attached). llvm-svn: 158937
* 1. fix null program output after some other changesAkira Hatanaka2012-06-213-9/+30
| | | | | | | | | 2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. llvm-svn: 158935
* Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc ↵Hal Finkel2012-06-211-1/+6
| | | | | | | | stores on PPC. Thanks to Tobias von Koch for pointing out this problem. llvm-svn: 158932
* fix build in C++11 mode.Nuno Lopes2012-06-211-7/+7
| | | | | | Thanks to Chandler for pointing out the problem. llvm-svn: 158928
* Fix potential crash if DAGCombine on stores sees a half typePete Cooper2012-06-211-1/+2
| | | | llvm-svn: 158927
* The inline asm operand modifier 'c' is suppose Jack Carter2012-06-212-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Substitute immediate value without immediate syntax Several Architectures such as x86 have local implementations of operand modifier 'c' which go beyond the above description slightly. To make use of the generic modifiers without overriding local implementation one can make a call to the base class method for AsmPrinter::PrintAsmOperand() in the locally derived method's "default" case in the switch statement. That way if it is already defined locally the generic version will never get called. This change is needed when test/CodeGen/generic/asm-large-immediate.ll failed on a native Mips board. The test was assuming a generic implementation was in place. Affected files: lib/Target/Mips/MipsAsmPrinter.cpp: Changed the default case to call the base method. lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'c' to the switch cases. test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter llvm-svn: 158925
* hopefully fix the buildbots: some tests have wrong definitions of malloc ↵Nuno Lopes2012-06-211-3/+5
| | | | | | and were crashing this code on 64 bits machines llvm-svn: 158923
OpenPOWER on IntegriCloud