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| author | Andrew Trick <atrick@apple.com> | 2012-06-22 03:58:51 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-22 03:58:51 +0000 |
| commit | 9c302673b22cef7bc326270226251fcf2ac97834 (patch) | |
| tree | b06a8ef8199ae55b58aaf06d6448466ba27245f7 /llvm/lib | |
| parent | f813086c8579472ca8d18af103c9c2d982139d0f (diff) | |
| download | bcm5719-llvm-9c302673b22cef7bc326270226251fcf2ac97834.tar.gz bcm5719-llvm-9c302673b22cef7bc326270226251fcf2ac97834.zip | |
Use "NoItineraries" for processors with no itineraries.
This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.
llvm-svn: 158963
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSchedule.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/MBlaze/MBlaze.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/MBlaze/MBlazeSchedule.td | 5 |
4 files changed, 2 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 9b0cb0c9e57..d332d20f80d 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -141,7 +141,7 @@ def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", FeatureAvoidPartialCPSR]>; class ProcNoItin<string Name, list<SubtargetFeature> Features> - : Processor<Name, GenericItineraries, Features>; + : Processor<Name, NoItineraries, Features>; // V4 Processors. def : ProcNoItin<"generic", []>; diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td index 45486fd0b6d..b9a07f1ee68 100644 --- a/llvm/lib/Target/ARM/ARMSchedule.td +++ b/llvm/lib/Target/ARM/ARMSchedule.td @@ -258,8 +258,6 @@ def IIC_VTBX4 : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. -def GenericItineraries : ProcessorItineraries<[], [], []>; - include "ARMScheduleV6.td" include "ARMScheduleA8.td" include "ARMScheduleA9.td" diff --git a/llvm/lib/Target/MBlaze/MBlaze.td b/llvm/lib/Target/MBlaze/MBlaze.td index b4edff0709e..c2888553c5e 100644 --- a/llvm/lib/Target/MBlaze/MBlaze.td +++ b/llvm/lib/Target/MBlaze/MBlaze.td @@ -50,7 +50,7 @@ def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true", // MBlaze processors supported. //===----------------------------------------------------------------------===// -def : Processor<"mblaze", MBlazeGenericItineraries, []>; +def : Processor<"mblaze", NoItineraries, []>; def : Processor<"mblaze3", MBlazePipe3Itineraries, []>; def : Processor<"mblaze5", MBlazePipe5Itineraries, []>; diff --git a/llvm/lib/Target/MBlaze/MBlazeSchedule.td b/llvm/lib/Target/MBlaze/MBlazeSchedule.td index 4a3ae5fc147..cd5691ce644 100644 --- a/llvm/lib/Target/MBlaze/MBlazeSchedule.td +++ b/llvm/lib/Target/MBlaze/MBlazeSchedule.td @@ -40,11 +40,6 @@ def IIC_WDC : InstrItinClass; def IIC_Pseudo : InstrItinClass; //===----------------------------------------------------------------------===// -// MBlaze generic instruction itineraries. -//===----------------------------------------------------------------------===// -def MBlazeGenericItineraries : ProcessorItineraries<[], [], []>; - -//===----------------------------------------------------------------------===// // MBlaze instruction itineraries for three stage pipeline. //===----------------------------------------------------------------------===// include "MBlazeSchedule3.td" |
