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* [x86] enable machine combiner reassociations for scalar double-precision addsSanjay Patel2015-07-091-0/+2
| | | | llvm-svn: 241871
* MIR Serialization: Serialize the virtual register definitions.Alex Lorenz2015-07-092-6/+62
| | | | | | | | | | | | The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 llvm-svn: 241868
* [LAA] Fix grammar in debug outputAdam Nemet2015-07-091-1/+1
| | | | llvm-svn: 241867
* [LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFCAdam Nemet2015-07-091-31/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT. NeedRTCheck says whether we need checks and CanDoRT whether we can generate the checks. The idea is to encode three states with these: Need/Can: (1) false/dont-care: no checks are needed (2) true/false: we need checks but can't generate them (3) true/true: we need checks and we can generate them This is pretty unnecessary since the caller (analyzeLoop) is only interested in whether we can generate the checks if we actually need them (i.e. 1 or 3). So this change cleans up to return just that (CanDoRTIfNeeded) and pulls all the underlying logic into canCheckPtrAtRT. By doing all this, we simplify analyzeLoop which is the complex function in LAA. There is further room for improvement here by using RtCheck.Need directly rather than a new local variable NeedRTCheck but that's for a later patch. llvm-svn: 241866
* [WinEH] Give up on using CSRs across 32-bit invokes for nowReid Kleckner2015-07-091-2/+17
| | | | | | | | | | | The runtime does not restore CSRs when transferring control back to the function handling the exception. According to the experts on IRC, LLVM's register allocator has no way to model register clobbers that only happen on one edge of the CFG. For now, don't worry about trying to use the meager three CSRs available on 32-bit X86 and just say that such invokes preserve nothing. llvm-svn: 241865
* Expose sjlj preparation through opt for my own debugging purposesReid Kleckner2015-07-091-0/+2
| | | | llvm-svn: 241864
* MIR Parser: Report an error when parsing machine function with an empty body.Alex Lorenz2015-07-091-0/+3
| | | | | | | | | | This commit adds a new error which is reported when the MIR Parser encounters a machine function without any machine basic blocks. The machine verifier expects that the machine functions have at least one MBB, and this error will prevent machine functions without MBBs from reaching the machine verifier and crashing with an assertion. llvm-svn: 241862
* AMDGPU: Add helper function for implicit parameter offsets.Tom Stellard2015-07-094-4/+28
| | | | | | Patch by: Zoltan Gilian llvm-svn: 241861
* Unbreak WebAssembly buildJF Bastien2015-07-094-26/+6
| | | | | | | | | | | | Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed. Reviewers: sunfish, joker.eph, echristo Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11084 llvm-svn: 241859
* [ImplicitNullChecks] Fix a memory leak.Sanjoy Das2015-07-091-1/+1
| | | | llvm-svn: 241851
* [ImplicitNullChecks] Be smarter in picking the memory op.Sanjoy Das2015-07-091-8/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change ImplicitNullChecks would only pick loads of the form: ``` test Reg, Reg jz elsewhere fallthrough: movl 32(Reg), Reg2 ``` but not (say) ``` test Reg, Reg jz elsewhere fallthrough: inc Reg3 movl 32(Reg), Reg2 ``` This change teaches ImplicitNullChecks to look through "unrelated" instructions like `inc Reg3` when searching for a load instruction to convert to a trapping load. Reviewers: atrick, JosephTremoulet, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11044 llvm-svn: 241850
* MIR Serialization: Serialize the simple MachineFrameInfo attributes.Alex Lorenz2015-07-092-0/+45
| | | | | | | | | | | | This commit serializes the 13 scalar boolean and integer attributes from the MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap, HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack, HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and HasMustTailInVarArgFunc. These attributes are serialized as part of the frameInfo YAML mapping, which itself is a part of the machine function's YAML mapping. llvm-svn: 241844
* llvm-ar: Pad the symbol table to 4 bytes.Rafael Espindola2015-07-091-2/+5
| | | | | | | It looks like ld64 requires it. With this we seem to be able to bootstrap using llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2). llvm-svn: 241842
* AMDGPU/R600: Return correct chain when lowering loadsMatt Arsenault2015-07-091-8/+2
| | | | | | The other LowerLOAD should be returning the correct chain. llvm-svn: 241839
* [IndVars] Try to use existing values in RewriteLoopExitValues.Sanjoy Das2015-07-091-2/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In RewriteLoopExitValues, before expanding out an SCEV expression using SCEVExpander, try to see if an existing LLVM IR expression already computes the value we're interested in. If so use that existing expression. Apart from reducing IndVars' reliance on the rest of the compilation pipeline, this also prevents IndVars from concluding some expressions as "high cost" when they're not. For instance, `InductiveRangeCheckElimination` often emits code of the following form: ``` len = umin(len_A, len_B) loop: ... if (i++ < len) goto loop outside_loop: use(i) ``` `SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`, since it thinks the value of `i` on loop exit, `len`, is a high cost expansion since it contains an `umax` in it. With this change, `IndVars` can see that it can re-use `len` instead of creating a new expression to compute `umin(len_A, len_B)`. I considered putting this cleverness in `SCEVExpander`, but I was worried that it may then have a deterimental effect on other passes that use it. So I decided it was better to just do this in the one place where it seems like an obviously good idea, with the intent of generalizing later if needed. Reviewers: atrick, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10782 llvm-svn: 241838
* Remove dead code from old 64-bit SEH loweringReid Kleckner2015-07-092-26/+0
| | | | llvm-svn: 241829
* Allow {e,r}bp as the target of {read,write}_register.Pat Gavlin2015-07-0911-17/+46
| | | | | | | | | | This patch allows the read_register and write_register intrinsics to read/write the RBP/EBP registers on X86 iff the targeted register is the frame pointer for the containing function. Differential Revision: http://reviews.llvm.org/D10977 llvm-svn: 241827
* fix an invisible bug when combining repeated FP divisorsSanjay Patel2015-07-091-2/+9
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG: r237046 ( http://reviews.llvm.org/rL237046 ): 1. When replacing a division node, it's not enough to RAUW. We should call CombineTo() to delete dead nodes and combine again. 2. Because we are changing the DAG, we can't return an empty SDValue after the transform. As the code comments say: Visitation implementation - Implement dag node combining for different node types. The semantics are as follows: Return Value: SDValue.getNode() == 0 - No change was made SDValue.getNode() == N - N was replaced, is dead and has been handled. otherwise - N should be replaced by the returned Operand. The new test case shows no difference with or without this patch, but it will crash if we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt. Differential Revision: http://reviews.llvm.org/D9893 llvm-svn: 241826
* [StackMap] Use lambdas to specify the sort and erase conditions. NFC.Juergen Ributzka2015-07-091-6/+14
| | | | llvm-svn: 241823
* [StackMap] Rename variables to be more consistent. NFC.Juergen Ributzka2015-07-091-40/+38
| | | | | | Rename a few variables and use auto for long iterator names. llvm-svn: 241822
* [StackMaps] Use emplace_back when possible. NFC.Juergen Ributzka2015-07-091-5/+5
| | | | llvm-svn: 241821
* AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with ↵Tom Stellard2015-07-091-1/+1
| | | | | | | | | one use This is convered by existing testcases and will be exposed by a future commit. llvm-svn: 241817
* AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()Tom Stellard2015-07-091-1/+4
| | | | | | | No test case for this. I ran into it while working on some improvements to SIShrinkInstructions.cpp. llvm-svn: 241816
* Basic support for BSD symbol tables in archives.Rafael Espindola2015-07-091-17/+39
| | | | | | | This could be optimized and for now we only produce __.SYMDEF and not "__.SYMDEF SORTED". llvm-svn: 241814
* [Hexagon] Add missing preamble to a source fileKrzysztof Parzyszek2015-07-091-0/+9
| | | | llvm-svn: 241813
* Remove redundant variable. NFC.Rafael Espindola2015-07-091-2/+1
| | | | llvm-svn: 241810
* Don't rely on the DepCands iteration order when constructing checking ↵Silviu Baranga2015-07-091-4/+26
| | | | | | | | | | | | | | | | | | | pointer groups Summary: The checking pointer group construction algorithm relied on the iteration on DepCands. We would need the same leaders across runs and the same iteration order over the underlying std::set for determinism. This changes the algorithm to process the pointers in the order in which they were added to the runtime check, which is deterministic. We need to update the tests, since the order in which pointers appear has changed. No new tests were added, since it is impossible to test for non-determinism. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11064 llvm-svn: 241809
* Add a helper to printing BE of LE depending on the format.Rafael Espindola2015-07-091-6/+10
| | | | | | | The gnu ar format uses BE numbers. The BSD one uses LE. Add a helper for one or the other. NFC for now, just removes some noise from the following patch. llvm-svn: 241808
* Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT userMehdi Amini2015-07-0916-18/+22
| | | | | | | A documentation for this function would be nice by the way. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241807
* Reapply fixed r241790: Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-093-18/+17
| | | | | | | | | | | | Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
* Extract printBSDMemberHeader.Rafael Espindola2015-07-091-22/+25
| | | | | | | It will get another use in the following patch. Also rename the other helper to printGNUSmallMemberHeader for consistency. llvm-svn: 241805
* [Hexagon] Add support for atomic RMW operationsKrzysztof Parzyszek2015-07-093-1/+59
| | | | llvm-svn: 241804
* [AArch64] Select SBFIZ or UBFIZ instead of left + right shiftsArnaud A. de Grandmaison2015-07-091-20/+16
| | | | | | And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology. llvm-svn: 241803
* [ARM] Thumb1 3 to 2 operand convertion for commutative operationsScott Douglass2015-07-091-3/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D11057 llvm-svn: 241802
* [ARM] Don't be overzealous converting Thumb1 3 to 2 operandsScott Douglass2015-07-091-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D11056 llvm-svn: 241801
* [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2Scott Douglass2015-07-091-2/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11055 llvm-svn: 241800
* [ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)Scott Douglass2015-07-091-42/+45
| | | | | | | | Also adds some test cases. Differential Revision: http://reviews.llvm.org/D11054 llvm-svn: 241799
* Add support for nest attribute to AArch64 backendRenato Golin2015-07-091-0/+5
| | | | | | | | | | | | | | | The nest attribute is currently supported on the x86 (32-bit) and x86-64 backends, but not on ARM (32-bit) or AArch64. This patch adds support for nest to the AArch64 backend. Register x18 is used by GCC for this purpose and hence is used here. As discussed on the GCC mailing list the register choice is an ABI issue and so choosing the same register as GCC means __builtin_call_with_static_chain is compatible. Patch by Stephen Cross. llvm-svn: 241794
* Add getSizeInBits function to the APFloat classTamas Berghammer2015-07-091-8/+15
| | | | | | | | | The newly added function returns the size of the specified floating point semantics in bits. Differential revision: http://reviews.llvm.org/D8413 llvm-svn: 241793
* Revert r241790: Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-093-18/+19
| | | | llvm-svn: 241792
* Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-093-19/+18
| | | | | | | | | | | | Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241790
* Extended syntax of vector version of getelementptr instruction.Elena Demikhovsky2015-07-093-22/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | The justification of this change is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/082989.html According to the current GEP syntax, vector GEP requires that each index must be a vector with the same number of elements. %A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets In this implementation I let each index be or vector or scalar. All vector indices must have the same number of elements. The scalar value will mean the splat vector value. (1) %A = getelementptr i8, i8* %ptr, <4 x i64> %offsets or (2) %A = getelementptr i8, <4 x i8*> %ptrs, i64 %offset In all cases the %A type is <4 x i8*> In the case (2) we add the same offset to all pointers. The case (1) covers C[B[i]] case, when we have the same base C and different offsets B[i]. The documentation is updated. http://reviews.llvm.org/D10496 llvm-svn: 241788
* [LAA] Fix line break in commentAdam Nemet2015-07-091-1/+1
| | | | llvm-svn: 241785
* [LAA] Rename IsRTNeeded to IsRTCheckAnalysisNeededAdam Nemet2015-07-091-6/+17
| | | | | | | | | | | | The original name was too close to NeedRTCheck which is what the actual memcheck analysis returns. This flag, as the new name suggests, is only used to whether to initiate that analysis. Also a comment is added to answer one question I had about this code for a long time. Namely, how does this flag differ from isDependencyCheckNeeded since they are seemingly set at the same time. llvm-svn: 241784
* Remove getDataLayout() from TargetSelectionDAGInfo (had no users)Mehdi Amini2015-07-0941-298/+27
| | | | | | | | | | | | | | | | | | Summary: Remove empty subclass in the process. This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren, ted Differential Revision: http://reviews.llvm.org/D11045 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241780
* Remove getDataLayout() from TargetLoweringMehdi Amini2015-07-0915-112/+120
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: yaron.keren, rafael, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11042 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241779
* Make isLegalAddressingMode() taking DataLayout as an argumentMehdi Amini2015-07-0923-61/+61
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11040 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241778
* Make getByValTypeAlignment() taking DataLayout as an argumentMehdi Amini2015-07-097-10/+15
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: yaron.keren, rafael, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11038 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241777
* Make TargetLowering::getShiftAmountTy() taking DataLayout as an argumentMehdi Amini2015-07-0924-141/+190
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11037 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241776
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-0970-1301/+1539
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D11028 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241775
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