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* Add a libLTO diagnostic handler that supports lto_get_error_message APIYunzhong Gao2015-11-111-8/+2
| | | | | | | | | | | | | | This is a follow-up from the previous discussion on the thread: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151019/307763.html The LibLTO lto_get_error_message() API reads error messages from a std::string sLastErrorString. Instead of passing this string around as an argument, this patch creates a diagnostic handler and then sends this handler to the constructor of LTOCodeGenerator. Differential Revision: http://reviews.llvm.org/D14313 llvm-svn: 252791
* [DAGCombiner] Improve zextload optimization.Geoff Berry2015-11-111-22/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Don't fold (zext (and (load x), cst)) -> (and (zextload x), (zext cst)) if (and (load x) cst) will match as a zextload already and has additional users. For example, the following IR: %load = load i32, i32* %ptr, align 8 %load16 = and i32 %load, 65535 %load64 = zext i32 %load16 to i64 store i32 %load16, i32* %dst1, align 4 store i64 %load64, i64* %dst2, align 8 used to produce the following aarch64 code: ldr w8, [x0] and w9, w8, #0xffff and x8, x8, #0xffff str w9, [x1] str x8, [x2] but with this change produces the following aarch64 code: ldrh w8, [x0] str w8, [x1] str x8, [x2] Reviewers: resistor, mcrosier Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14340 llvm-svn: 252789
* dwarfdump: DWP type unit index dumping skeletonDavid Blaikie2015-11-111-0/+10
| | | | llvm-svn: 252786
* Refactoring and fix another instance of asan errorXinliang David Li2015-11-111-5/+10
| | | | llvm-svn: 252783
* Format my previous commitDavid Blaikie2015-11-112-6/+5
| | | | llvm-svn: 252782
* dwarfdump: First piece of support for DWP dumpingDavid Blaikie2015-11-113-0/+52
| | | | | | Just a tiny piece of index dumping - the header in this instance. llvm-svn: 252781
* [WinEH] Only generate UnwindHelp slot for MSVCXXJoseph Tremoulet2015-11-111-12/+12
| | | | | | | | | | | | Summary: Other personalities don't use this special frame slot. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14580 llvm-svn: 252778
* Support: Recognize Borland DWARF extensions.Dawn Perchik2015-11-111-0/+25
| | | | | | | | | | | This patch adds DWARF values for the Delphi language and Borland C++ language extensions. Reviewed by: dblaikie Subscribers: llvm-commits, majnemer Differential Revision: http://reviews.llvm.org/D14522 llvm-svn: 252776
* Add target preference for GatherAllAliases max depthMatt Arsenault2015-11-112-1/+2
| | | | llvm-svn: 252775
* Reverting r252760Colin LeMahieu2015-11-111-14/+6
| | | | llvm-svn: 252770
* clang-format lib/CodeGen/AsmPrinter/DwarfCompileUnit.cppDehao Chen2015-11-111-7/+8
| | | | llvm-svn: 252769
* Emit discriminator for inlined callsites.Dehao Chen2015-11-112-0/+3
| | | | | | | | | | | | Summary: Inlined callsites need to be emitted in debug info so that sample profile can be annotated to the correct inlined instance. Reviewers: dnovillo, dblaikie Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D14511 llvm-svn: 252768
* SamplePGO - Fix PR 25482 - Do not rely on llvm.dbg.cu for discriminatorsDiego Novillo2015-11-111-2/+2
| | | | | | | | | | | | | | | The discriminators pass relied on the presence of llvm.dbg.cu to decide whether to add discriminators, but this fails in the case where debug info is only enabled partially when -fprofile-sample-use is active. The reason llvm.dbg.cu is not present in these cases is to prevent codegen from emitting debug info (as it is only used for the sample profile pass). This changes the discriminators pass to also emit discriminators even when debug info is not being emitted. llvm-svn: 252763
* [Symbolizer]: Add -pretty-print optionHemant Kulkarni2015-11-111-6/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D13671 llvm-svn: 252760
* [MIPS] add overrides for isCheapToSpeculateCttz() and isCheapToSpeculateCtlz()Sanjay Patel2015-11-112-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS32 has instructions for efficient count-leading/trailing-zeros, so this should be considered a cheap operation (and therefore fair game for speculation) for any MIPS32 implementation. The net result of allowing this speculation for the regression tests in this patch is that we get this code: ctlz: jr $ra clz $2, $4 cttz: addiu $1, $4, -1 not $2, $4 and $1, $2, $1 clz $1, $1 addiu $2, $zero, 32 jr $ra subu $2, $2, $1 Instead of: ctlz: beqz $4, $BB0_2 addiu $2, $zero, 32 clz $2, $4 $BB0_2: jr $ra nop cttz: beqz $4, $BB1_2 addiu $2, $zero, 32 addiu $1, $4, -1 not $2, $4 and $1, $2, $1 clz $1, $1 addiu $2, $zero, 32 subu $2, $2, $1 $BB1_2: jr $ra nop See D14469 for the larger motivation. Differential Revision: http://reviews.llvm.org/D14500 llvm-svn: 252755
* Properly fix unused variable in disable-assert builds.Diego Novillo2015-11-111-1/+3
| | | | | | | | I missed the side-effects of ParseBFI in my previous attempt (r252748). Thanks dblaikie for the suggestion of adding a void use of the unused variable instead. llvm-svn: 252751
* Remove unused variable in disable-assert builds. NFC.Diego Novillo2015-11-111-2/+1
| | | | llvm-svn: 252748
* Visibly fail if attempting to encode register AH,BH,CH,DH in a REX-prefixed ↵Douglas Katzman2015-11-111-0/+7
| | | | | | | | | instruction. Differential Revision: http://reviews.llvm.org/D13316 Fixes PR25003 llvm-svn: 252743
* [ARM] Combine BFIs togetherJames Molloy2015-11-111-2/+109
| | | | | | If we have a chain of BFIs, we may be able to combine several together into one merged BFI. We can do this if the "from" bits from one BFI OR'd with the "from" bits from the other BFI form a contiguous range, and the same with the "to" bits. llvm-svn: 252740
* [SLP] Enable -slp-vectorize-hor by default.Charlie Turner2015-11-111-1/+1
| | | | | | | | | | | Measurements primarily on AArch64 have shown this feature does not significantly effect compile-time. The are no significant perf changes in LNT, but for AArch64 at least, there are wins in third party benchmarks. As discussed on llvm-dev, we're going to try turning this on by default and see how other targets react to the change. llvm-svn: 252733
* Silencing a signed vs unsigned type mismatch warning.Aaron Ballman2015-11-111-1/+1
| | | | llvm-svn: 252732
* Silencing nine warnings for "enumeral and non-enumeral type in conditional ↵Aaron Ballman2015-11-111-10/+18
| | | | | | expression"; NFC. llvm-svn: 252728
* [X86] Replace LEAs with INC/DEC when profitableMichael Kuperstein2015-11-111-8/+79
| | | | | | | | | If possible and profitable, replace lea %reg, 1(%reg) and lea %reg, -1(%reg) with inc %reg and dec %reg respectively. Patch by: anton.nadolsky@intel.com Differential Revision: http://reviews.llvm.org/D14059 llvm-svn: 252722
* [ASan] Enable optional ASan recovery.Yury Gribov2015-11-111-18/+33
| | | | | | Differential Revision: http://reviews.llvm.org/D14242 llvm-svn: 252719
* [X86] Fix feature flags on some MMX register instructions that really were ↵Craig Topper2015-11-111-2/+13
| | | | | | introduced with SSE or SSE2. llvm-svn: 252709
* [X86] Remove redundant MMX isel patterns.Craig Topper2015-11-111-4/+0
| | | | llvm-svn: 252708
* [WebAssembly] Support non-legal argument and return types.Dan Gohman2015-11-113-79/+127
| | | | llvm-svn: 252687
* [MC] Use LShr for constant evaluation of ">>" on non-arm64 darwin.Ahmed Bougacha2015-11-113-11/+1
| | | | | | | Follow-up to r235963: this matches other assemblers and is less unexpected (e.g. PR23227). llvm-svn: 252681
* MachineInstr: addRegisterDefReadUndef() => setRegisterDefReadUndef()Matthias Braun2015-11-112-3/+3
| | | | | | This way we can not only add but also remove read undef flags. llvm-svn: 252678
* AMDGPU: Print more fields in commentsMatt Arsenault2015-11-111-3/+14
| | | | llvm-svn: 252677
* [ValueTracking] Remove untested / unreachable code, NFCSanjoy Das2015-11-111-18/+5
| | | | | | | | Right now isTruePredicate is only ever called with Pred == ICMP_SLE or ICMP_ULE, and the ICMP_SLT and ICMP_ULT cases are dead. This change removes the untested dead code so that the function is not misleading. llvm-svn: 252676
* AMDGPU: Remove dead codeMatt Arsenault2015-11-111-33/+2
| | | | llvm-svn: 252675
* AMDGPU: Set isAllocatable = 0 on VS_32/VS_64Matt Arsenault2015-11-113-16/+6
| | | | llvm-svn: 252674
* [ValueTracking] Teach isImpliedCondition a new bitwise trickSanjoy Das2015-11-101-0/+30
| | | | | | | | | | | | | | | | | | | Summary: This change teaches isImpliedCondition to prove things like (A | 15) < L ==> (A | 14) < L if the low 4 bits of A are known to be zero. Depends on D14391 Reviewers: majnemer, reames, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14392 llvm-svn: 252673
* [ValueTracking] Use m_APInt instead of m_ConstantInt, NFCSanjoy Das2015-11-101-7/+8
| | | | | | | | This change would add functionality if isImpliedCondition worked on vector types; but since it bail out on vector predicates this change is an NFC. llvm-svn: 252672
* TableGen: Emit LaneMask for register classes without subregisters as ~0uMatthias Braun2015-11-101-10/+13
| | | | | | | This makes it slightly easier to handle classes with and without subregister uniformly. llvm-svn: 252671
* [WinEH] Insert the MBB for EH_RESTORE after the catchretReid Kleckner2015-11-101-1/+1
| | | | | | | Inserting it before the target block could be bad, we might already have a fallthrough edge to it. llvm-svn: 252670
* [libFuzzer] add UninstrumentedTest.cpp (missing from a previous commit)Kostya Serebryany2015-11-101-0/+8
| | | | llvm-svn: 252658
* [WebAssembly] Remove special cases for things that are no longer special. NFC.Dan Gohman2015-11-101-16/+0
| | | | llvm-svn: 252656
* Add PPCMIPeephole.cpp to CMakeLists.txtBill Schmidt2015-11-101-0/+1
| | | | llvm-svn: 252654
* [WebAssembly] Support for floating point min and max.Dan Gohman2015-11-102-7/+6
| | | | llvm-svn: 252653
* [PowerPC] Add an MI SSA peephole pass.Bill Schmidt2015-11-103-0/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a pass for doing PowerPC peephole optimizations at the MI level while the code is still in SSA form. This allows for easy modifications to the instructions while depending on a subsequent pass of DCE. Both passes are very fast due to the characteristics of SSA. At this time, the only peepholes added are for cleaning up various redundancies involving the XXPERMDI instruction. However, I would expect this will be a useful place to add more peepholes for inefficiencies generated during instruction selection. The pass is placed after VSX swap optimization, as it is best to let that pass remove unnecessary swaps before performing any remaining clean-ups. The utility of these clean-ups are demonstrated by changes to four existing test cases, all of which now have tighter expected code generation. I've also added Eric Schweiz's bugpoint-reduced test from PR25157, for which we now generate tight code. One other test started failing for me, and I've fixed it (test/Transforms/PlaceSafepoints/finite-loops.ll) as well; this is not related to my changes, and I'm not sure why it works before and not after. The problem is that the CHECK-NOT: of "statepoint" from test1 fails because of the "statepoint" in test2, and so forth. Adding a CHECK-LABEL in between keeps the different occurrences of that string properly scoped. llvm-svn: 252651
* Ensure ModuleLinker materializes complete comdat groupsTeresa Johnson2015-11-101-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The module linker lazy links some "discardable if unused" global values (e.g. linkonce), materializing and linking them only if they are referenced in the module. If a comdat group contains a linkonce member that is not referenced, however, it would not be materialized and linked, leading to an incomplete comdat group. If there are other object files not part of the same LTO link that also define and use that comdat group, the linker may select the incomplete group leading to link time unsats. To solve this, whenever a global value body is linked, make sure we materialize any other members of the same comdat group that are not yet materialized. This ensures they are in the lazy link list and get linked as well. Added new test and adjusted old test to remove parts that didn't make sense with fix. Reviewers: rafael Subscribers: dexonsmith, davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D14516 llvm-svn: 252647
* [IR] Make {Call,Invoke}::cloneImpl aware of operand bundlesSanjoy Das2015-11-101-0/+8
| | | | | | | | | This was an omission in the patch that landed initial support for operand bundles. So far we haven't hit this, but we will once the inliner is able to inline calls to functions that contain calls with operand bundles. llvm-svn: 252645
* [OperandBundles] Identify operand bundles with both their names and IDsSanjoy Das2015-11-102-2/+2
| | | | | | | No code uses this functionality yet. This change just exposes information / structure that was already present. llvm-svn: 252644
* less indent; NFCISanjay Patel2015-11-101-46/+47
| | | | llvm-svn: 252643
* [ARM] add overrides for isCheapToSpeculateCttz() and isCheapToSpeculateCtlz()Sanjay Patel2015-11-102-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM V6T2 has instructions for efficient count-leading/trailing-zeros, so this should be considered a cheap operation (and therefore fair game for speculation) for any ARM V6T2 implementation. The net result of allowing this speculation for the regression tests in this patch is that we get this code: ctlz: clz r0, r0 bx lr cttz: rbit r0, r0 clz r0, r0 bx lr Instead of: ctlz: cmp r0, #0 moveq r0, #32 clzne r0, r0 bx lr cttz: cmp r0, #0 moveq r0, #32 rbitne r0, r0 clzne r0, r0 bx lr This will help solve a general speculation/despeculation problem noted in PR24818: https://llvm.org/bugs/show_bug.cgi?id=24818 Differential Revision: http://reviews.llvm.org/D14469 llvm-svn: 252639
* LegalizeDAG: Implement promote for scalar_to_vectorMatt Arsenault2015-11-101-0/+28
| | | | | | | | | | | This allows avoiding the default Expand behavior which introduces stack usage. Bitcast the scalar and replace the missing elements with undef. This is covered by existing tests and used by a future commit which makes 64-bit vectors legal types on AMDGPU. llvm-svn: 252632
* LegalizeDAG: Implement promote for insert_vector_eltMatt Arsenault2015-11-101-1/+52
| | | | | | | This is covered by existing tests and used by a future commit which makes 64-bit vectors legal types on AMDGPU. llvm-svn: 252631
* LegalizeDAG: Implement promote for extract_vector_eltMatt Arsenault2015-11-101-4/+58
| | | | | | | | | | This is for AMDGPU to implement v2i64 extract as extract of half of a v4i32. This is covered by existing tests and used by a future commit which makes 64-bit vectors legal types on AMDGPU. llvm-svn: 252630
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