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* Fixed the ability to recursively get an attribute value from a DWARFDie.Greg Clayton2017-11-271-10/+9
| | | | | | | | The previous implementation would only look 1 DW_AT_specification or DW_AT_abstract_origin deep. This means DWARFDie::getName() would fail in certain cases. I ran into such a case while creating a tool that used the LLVM DWARF parser to generate a symbolication format so I have seen this in the wild. Differential Revision: https://reviews.llvm.org/D40156 llvm-svn: 319104
* [X86] Remove lines that set v8f32 FP_ROUND/FP_EXTEND to Legal under AVX512. NFCICraig Topper2017-11-271-2/+0
| | | | | | We don't do this for narrow vectors under AVX or SSE features. We also don't set them to Expand like we do for many vectors op. Nor does TargetLoweringBase.cpp. This leads me to believe these default to Legal. llvm-svn: 319103
* [Mem2Reg] Clang-format unformatted parts of this file. NFCI.Davide Italiano2017-11-271-28/+23
| | | | llvm-svn: 319097
* [SROA] Propagate !range metadata when moving loads.Davide Italiano2017-11-273-32/+168
| | | | | | | | | | | | | This tries to propagate !range metadata to a pre-existing load when a load is optimized out. This is done instead of adding an assume because converting loads to and from assumes creates a lot of IR. Patch by Ariel Ben-Yehuda. Differential Revision: https://reviews.llvm.org/D37216 llvm-svn: 319096
* [PartiallyInlineLibCalls][x86] add TTI hook to allow sqrt inlining to depend ↵Sanjay Patel2017-11-274-5/+19
| | | | | | | | | | | on arg rather than result This should fix PR31455: https://bugs.llvm.org/show_bug.cgi?id=31455 Differential Revision: https://reviews.llvm.org/D28314 llvm-svn: 319094
* [PowerPC] Remove redundant TOC savesZaara Syeda2017-11-273-2/+87
| | | | | | | | | | This patch adds a peep hole optimization to remove any redundant toc save instructions added as part of the call sequence for indirect calls. It removes any toc saves within a function that are dominated by another toc save. Differential Revision: https://reviews.llvm.org/D39736 llvm-svn: 319087
* [SelectionDAG] Add a debug message when vector_shuffle nodes are created.Craig Topper2017-11-271-1/+3
| | | | | | We print a debug message when most nodes are created, but getVectorShuffle was missing. llvm-svn: 319085
* Inliner: Don't mark notail calls with the 'tail' attributeArnold Schwaighofer2017-11-271-1/+2
| | | | | | | | | | | | enum TailCallKind { TCK_None = 0, TCK_Tail = 1, TCK_MustTail = 2, TCK_NoTail = 3 }; TCK_NoTail is greater than TCK_Tail so taking the min does not do the correct thing. rdar://35639547 llvm-svn: 319075
* [BinaryStream] Support growable streams.Zachary Turner2017-11-273-13/+14
| | | | | | | | | The existing library assumed that a stream's length would never change. This makes some things simpler, but it's not flexible enough for what we need, especially for writable streams where what you really want is for each call to write to actually append. llvm-svn: 319070
* [X86] Remove an unused isel pattern that looked for pshufd with v4f32 type.Craig Topper2017-11-271-12/+0
| | | | | | I don't believe our current lowering/combining would ever produce such a node. We only produce integer typed pshufds. llvm-svn: 319068
* [InstCombine] use 'auto' with 'dyn_cast'; NFCSanjay Patel2017-11-271-3/+2
| | | | llvm-svn: 319067
* [X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.Craig Topper2017-11-271-1/+1
| | | | | | I don't have a good test case for this at the moment. I was playing around with a change in legalizing and triggered this code to produce a PSHUFD with sse1 only. llvm-svn: 319066
* [X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with ↵Simon Pilgrim2017-11-272-20/+29
| | | | | | | | SSE_PACK/SSE_PMADD schedule classes llvm-svn: 319065
* [Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek2017-11-272-27/+14
| | | | llvm-svn: 319064
* [X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over ↵Craig Topper2017-11-271-1/+1
| | | | | | | | | | 512 bits long when AVX512 is enabled. Similar for vXi16/vXi8 with BWI. Any vector larger than 512 bits will be split to 512 bits during legalization. But without this we will fold sexts with them before that making it difficult to recover leading to scalarization. llvm-svn: 319059
* [X86][SSE] Fix roundpd instructions to correctly use IIC_SSE_ROUNDPD_* ↵Simon Pilgrim2017-11-271-2/+2
| | | | | | itineraries llvm-svn: 319054
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-273-6/+6
| | | | | | | | | See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433 Differential Revision: https://reviews.llvm.org/D40493 Reviewers: artem.tamazov, SamWot, arsenm llvm-svn: 319050
* [Power9] Improvements to vector extract with variable index exploitationZaara Syeda2017-11-271-22/+174
| | | | | | | | | | This patch extends on to rL307174 to not use the power9 vector extract with variable index instructions when extracting word element 1. For such cases, the existing selection of MFVSRWZ provides a better sequence. Differential Revision: https://reviews.llvm.org/D38287 llvm-svn: 319049
* [X86][AVX512] Tag AVX512 sqrt instructions with SSE_SQRT schedule classesSimon Pilgrim2017-11-271-29/+32
| | | | llvm-svn: 319045
* [llvm-dwarfdump] Display DW_AT_high_pc as absolute valueJonas Devlieghere2017-11-271-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | DWARF4 relative DW_AT_high_pc values are now displayed as absolute addresses. The relative value is only shown when explicitly dumping the forms, i.e. in show-form or verbose mode. ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x00000019) ``` becomes ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x0000000000000062) ``` Differential revision: https://reviews.llvm.org/D40317 rdar://35416943 llvm-svn: 319044
* [InstSimplify] use m_APFloat to simplify fcmp folds; NFCISanjay Patel2017-11-271-13/+7
| | | | llvm-svn: 319043
* [DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave2017-11-271-2/+0
| | | | | | | | | | | | | | | | Summary: Now that store-merge is only generates type-safe stores, do a second pass just before instruction selection to allow lowered intrinsics to be merged as well. Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33675 llvm-svn: 319036
* [X86] Add INVLPGA to the existing INVLPG schedulingSimon Pilgrim2017-11-271-3/+4
| | | | llvm-svn: 319031
* [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRCPetar Jovanovic2017-11-272-5/+5
| | | | | | | | | | | | | | | Make the print format consistent with other assembler instructions. Adding a tab character instead of space in asmstring of Ext and Ins instructions. Removing space around the tab character for JALRC and replacing space with tab in JRC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38144 llvm-svn: 319030
* [Support] Fix locking of shared variable in threadpoolJan Korous2017-11-271-1/+1
| | | | llvm-svn: 319027
* [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsicsVedran Miletic2017-11-272-0/+32
| | | | | | | | | | | | | | AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI. Reviewers: arsenm, jvesely Subscribers: tstellar Differential Revision: https://reviews.llvm.org/D29942 llvm-svn: 319025
* [CGP] Fix handling of null pointer values in optimizeMemoryInstJohn Brawn2017-11-271-9/+7
| | | | | | | | | | | The current way that trivial addressing modes are detected incorrectly thinks that null pointers are non-trivial, leading to an infinite loop where we keep duplicating the same select. Fix this by aware of null when deciding if an addressing mode is trivial. Differential Revision: https://reviews.llvm.org/D40447 llvm-svn: 319019
* [X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule classSimon Pilgrim2017-11-2710-52/+75
| | | | | | | | | | As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general). Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes. Differential Revision: https://reviews.llvm.org/D40351 llvm-svn: 319016
* [ARM] Fix an off-by-one error when restoring LR for 16-bit ThumbMomchil Velikov2017-11-271-1/+1
| | | | | | | | | | | | | | The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to restore LR from. The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) + count of the popped registers. We need to load LR from just past the last register, hence the correct offset should be either getNumOperands() - 4 and getNumExplicitOperands() - 2 (multiplied by 4). Differential revision: https://reviews.llvm.org/D40305 llvm-svn: 319014
* Update BTVER2 sched numbers for SSE42 string instructions.Andrew V. Tischenko2017-11-271-24/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D39846 llvm-svn: 319013
* [SelectionDAG] Teach SplitVecRes_SETCC to call GetSplitVector if the ↵Craig Topper2017-11-271-3/+12
| | | | | | operands have already been split. llvm-svn: 319010
* [SelectionDAG] Fix function name in comment. NFCCraig Topper2017-11-271-2/+2
| | | | llvm-svn: 319009
* [X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.Craig Topper2017-11-261-2/+1
| | | | | | The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert. llvm-svn: 319006
* [X86][3DNow] Add 3DNow! instruction itinerary and scheduling classesSimon Pilgrim2017-11-262-37/+84
| | | | llvm-svn: 319005
* [X86][3DNow] Remove unused I3DNow_binop_rm/I3DNow_conv_rm templates. NFCISimon Pilgrim2017-11-261-11/+0
| | | | llvm-svn: 319000
* [X86][MMX] Add IIC_MMX_MOVMSK instruction itinerary classSimon Pilgrim2017-11-263-2/+4
| | | | llvm-svn: 318999
* [SCEV] Adding a check on outgoing branches of a terminator instr for ↵Jatin Bhateja2017-11-261-10/+13
| | | | | | | | | | | | | | | | | | | | | | SCEVBackedgeConditionFolder, NFC. Summary: For a given loop, getLoopLatch returns a non-null value when a loop has only one latch block. In the modified context adding an assertion to check that both the outgoing branches of a terminator instruction (of latch) does not target same header. + few minor code reorganization. Reviewers: jbhateja Reviewed By: jbhateja Subscribers: sanjoy Differential Revision: https://reviews.llvm.org/D40460 llvm-svn: 318997
* Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon2017-11-2610-13/+98
| | | | | | | | | | | | | | | | | | Shadow stack solution introduces a new stack for return addresses only. The HW has a Shadow Stack Pointer (SSP) that points to the next return address. If we return to a different address, an exception is triggered. The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP). The intrinsics are mapped to new instruction set that implements CET mechanism. The patch also includes initial infrastructure support for IBT. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40223 Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4 llvm-svn: 318996
* [x86][icelake]GFNICoby Tayree2017-11-2611-3/+175
| | | | | | | | | | galois field arithmetic (GF(2^8)) insns: gf2p8affineinvqb gf2p8affineqb gf2p8mulb Differential Revision: https://reviews.llvm.org/D40373 llvm-svn: 318993
* [SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr.Jatin Bhateja2017-11-261-2/+1
| | | | | | | | | | | | | | | | | Summary: For a given loop, getLoopLatch returns a non-null value when a loop has only one latch block. In the modified context a check on both the outgoing branches of a terminator instruction (of latch) to same header is redundant. Reviewers: jbhateja Reviewed By: jbhateja Subscribers: sanjoy Differential Revision: https://reviews.llvm.org/D40460 llvm-svn: 318991
* [X86] Add separate intrinsics for scalar FMA4 instructions.Craig Topper2017-11-258-24/+56
| | | | | | | | | | | | | | | | | | | | | | | Summary: These instructions zero the non-scalar part of the lower 128-bits which makes them different than the FMA3 instructions which pass through the non-scalar part of the lower 128-bits. I've only added fmadd because we should be able to derive all other variants using operand negation in the intrinsic header like we do for AVX512. I think there are still some missed negate folding opportunities with the FMA4 instructions in light of this behavior difference that I hadn't noticed before. I've split the tests so that we can use different intrinsics for scalar testing between the two. I just copied the tests split the RUN lines and changed out the scalar intrinsics. fma4-fneg-combine.ll is a new test to make sure we negate the fma4 intrinsics correctly though there are a couple TODOs in it. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39851 llvm-svn: 318984
* [X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is ↵Craig Topper2017-11-254-14/+35
| | | | | | | | | | | | | | | | | | | disabled. Allow gather on SKX/CNL/ICL when AVX512 is disabled by using AVX2 instructions. Summary: This adds a new fast gather feature bit to cover all CPUs that support fast gather that we can use independent of whether the AVX512 feature is enabled. I'm only using this new bit to qualify AVX2 codegen. AVX512 is still implicitly assuming fast gather to keep tests working and to match the scatter behavior. Test command lines have been added for these two cases. Reviewers: magabari, delena, RKSimon, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40282 llvm-svn: 318983
* [SelectionDAG] Remove some dead code from vector scalaringCraig Topper2017-11-251-16/+1
| | | | | | | | | | | | | | | | | Summary: Currently ScalarizeVecRes_SETCC checks for the result type being a vector and jumps to ScalarizeVecRes_VSETCC. But if we're scalarizing a vector result, aren't we guaranteed to be looking at a vector type? This patch deletes the current ScalarizeVecRes_SETCC and renames ScalarizeVecRes_VSETCC to ScalarizeVecRes_SETCC. Reviewers: RKSimon, arsenm, eladcohen, zvi Reviewed By: RKSimon Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D40452 llvm-svn: 318982
* Add BTVER2 sched support for SHLD/SHRD.Andrew V. Tischenko2017-11-251-0/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D40124 llvm-svn: 318977
* [X86] Simplify some code in combineSetCC. NFCICraig Topper2017-11-251-10/+6
| | | | | | Make the condition for doing a std::swap simpler so we don't have to repeat the full checks. llvm-svn: 318970
* [X86] Qualify some vector specific code with VT.isVector(). NFCICraig Topper2017-11-251-2/+2
| | | | | | Other checks inside require a build_vector, but we this lets us stop earlier and makes the code more clear. llvm-svn: 318969
* [X86] Support folding to andnps with SSE1 only.Craig Topper2017-11-251-1/+4
| | | | | | With SSE1 only, we emit FAND and FXOR nodes for v4f32. llvm-svn: 318968
* [X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into ↵Craig Topper2017-11-251-6/+31
| | | | | | | | | | FAND/FOR/FXOR whe only SSE1 is available. v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise. This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header. llvm-svn: 318967
* Recommit r318963 "[APInt] Don't print debug messages from the APInt knuth ↵Craig Topper2017-11-241-0/+10
| | | | | | | | | | | | | | division algorithm by default" The previous commit had the condition in the do/while backwards. Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log. This adds a new preprocessor flag to enable the prints in the knuth division code in APInt. Differential Revision: https://reviews.llvm.org/D40404 llvm-svn: 318966
* [X86] Prevent using X * rsqrt(X) to approximate sqrt when only sse1 is enabled.Craig Topper2017-11-241-1/+4
| | | | | | | | This optimization can occur after type legalization and emit a vselect with v4i32 type. But that type is not legal with sse1. This ultimately gets scalarized by the second type legalization that runs after vector op legalization, but that's really intended to handle the scalar types that might be introduced by legalizing vector ops. For now just stop this from happening by disabling the optimization with sse1. llvm-svn: 318965
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