| Commit message (Collapse) | Author | Age | Files | Lines |
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for ELF to work.
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0,
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission
llvm-svn: 78129
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Add a comment explaining why.
llvm-svn: 78128
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address from the reverse mapping, and add a test that this works now.
llvm-svn: 78127
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llvm-svn: 78126
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llvm-svn: 78125
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yet, but there will be in the near future.
llvm-svn: 78122
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matches what the comment says, and it avoids spurious BitCast
instructions for Argument values.
llvm-svn: 78121
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and 126 if it is not executable.
llvm-svn: 78120
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llvm-svn: 78119
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llvm-svn: 78118
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llvm-svn: 78116
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header, to make LLVMContextImpl.h
not hideous. Also, fix some MSVC compile errors.
llvm-svn: 78115
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For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
llvm-svn: 78109
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This fixes PR4528.
llvm-svn: 78107
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scavenger.
Imp-def is *not* allowed to redefine a live register.
Imp-use is *not* allowed to use a dead register.
llvm-svn: 78106
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llvm-svn: 78105
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llvm-svn: 78104
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still get "intel syntax" instructions from llc with
-x86-asm-syntax=intel
llvm-svn: 78103
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llvm-svn: 78101
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distinguish that the result is errno, so it can't use it to provide more
information about the error (it also exposes the numeric value of errno).
llvm-svn: 78098
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llvm-svn: 78097
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the masm backend. If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.
llvm-svn: 78096
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For an undef operand, MO.getReg() is meaningless and we should not use it.
Undef operands should be skipped entirely.
llvm-svn: 78095
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of registers.
When LowerExtract eliminates an EXTRACT_SUBREG with a kill flag, it moves the
kill flag to the place where the sub-register is killed. This can accidentally
overlap with the use of a sibling sub-register, and we have trouble.
In the test case we have this code:
Live Ins: %R0 %R1 %R2
%R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
%R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
%R1L<def> = EXTRACT_SUBREG %R1<kill>, 1
%R0L<def> = EXTRACT_SUBREG %R0<kill>, 1
%R0H<def> = ADD16 %R2H<kill>, %R2L<kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>
subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: eliminated!
subreg: killed here: %R0H<def> = ADD16 %R2H, %R2L, %R2<imp-use,kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>
The kill flag on %R2 is moved to the last instruction, and the live range overlaps with the definition of %R2H:
*** Bad machine code: Redefining a live physical register ***
- function: f
- basic block: 0x18358c0 (#0)
- instruction: %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
Register R2H was defined but already live.
The fix is to replace EXTRACT_SUBREG with IMPLICIT_DEF instead of eliminating
it completely:
subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: replace by: %R2L<def> = IMPLICIT_DEF %R2<kill>
Note that these IMPLICIT_DEF instructions survive to the asm output. It is
necessary to fix the stack-color-with-reg test case because of that.
llvm-svn: 78093
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Implicit operands no longer get a free pass: Imp-use requires a live register
and imp-def requires a dead register.
There is also no special rule allowing redefinition of a sub-register when the
super-register is live. The super register must have imp-kill+imp-def operands
instead.
llvm-svn: 78090
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The only exception is CC.
llvm-svn: 78089
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llvm-svn: 78086
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llvm-svn: 78085
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llvm-svn: 78082
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to enable. Added patterns for some binary FP operations.
llvm-svn: 78081
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killed by another operand.
There is probably a better fix. Either 1) scavenger can look at other operands, or
2) livevariables can be smarter about kill markers. Patches welcome.
llvm-svn: 78072
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llvm-svn: 78070
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__TEXT,__ustring section on darwin.
llvm-svn: 78068
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it is just being used as a prefix, so forward substitute it directly.
llvm-svn: 78067
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section on ELF targets.
llvm-svn: 78066
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llvm-svn: 78060
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llvm-svn: 78059
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ldm / stm.
llvm-svn: 78057
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This fixes PR4666.
llvm-svn: 78056
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add new concrete versions for 1/2/4-byte mergable strings.
These are not actually created yet.
llvm-svn: 78055
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llvm-svn: 78053
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around in a tree I forgot about.
llvm-svn: 78048
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llvm-svn: 78047
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llvm-svn: 78043
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llvm-svn: 78035
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llvm-svn: 78034
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interleaved (using appropriate BLOCK_IDs) otherwise ValuePtrs index gets out of sync.
llvm-svn: 78033
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faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
llvm-svn: 78032
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llvm-svn: 78031
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This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
llvm-svn: 78030
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