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* Constify MCSymbol* parameters to DwarfDebug::attachLowHighPC.Frederic Riss2014-08-282-3/+3
| | | | llvm-svn: 216681
* Fix a logic bug in x86 vector codegen: sext (zext (x) ) != sext (x) (PR20472).Sanjay Patel2014-08-281-25/+11
| | | | | | | | | | | | | | | | | Remove a block of code from LowerSIGN_EXTEND_INREG() that was added with: http://llvm.org/viewvc/llvm-project?view=revision&revision=177421 And caused: http://llvm.org/bugs/show_bug.cgi?id=20472 (more analysis here) http://llvm.org/bugs/show_bug.cgi?id=18054 The testcases confirm that we (1) don't remove a zext op that is necessary and (2) generate a pmovz instead of punpck if SSE4.1 is available. Although pmovz is 1 byte longer, it allows folding of the load, and so saves 3 bytes overall. Differential Revision: http://reviews.llvm.org/D4909 llvm-svn: 216679
* Do not introduce new shuffle patterns after operation legalization if ↵Owen Anderson2014-08-281-2/+1
| | | | | | | | | SHUFFLE_VECTOR was marked custom. The target independent DAG combine has no way to know if the shuffles it is introducing are ones that the target could support or not. llvm-svn: 216678
* Janitorial services: "Don’t duplicate function or class name at the ↵Sanjay Patel2014-08-281-134/+119
| | | | | | beginning of the comment." llvm-svn: 216674
* Remove local TLI vars that are just duplicates of the class var. No ↵Sanjay Patel2014-08-281-2/+0
| | | | | | functional change. llvm-svn: 216673
* Use local vars to improve readability. No functional change.Sanjay Patel2014-08-281-42/+37
| | | | | | | Completes what was started in r216611 and r216623. Used const refs instead of pointers; not sure if one is preferable to the other. llvm-svn: 216672
* Minor spelling correction.Sid Manning2014-08-281-1/+1
| | | | | | | | Reviewers: adasgupt, jverma, sidneym Differential Revision: http://reviews.llvm.org/D5025 llvm-svn: 216667
* Silence a -Wsign-compare warning. NFC.Aaron Ballman2014-08-281-1/+1
| | | | llvm-svn: 216666
* [PBQP] Only output debug information when requestedArnaud A. de Grandmaison2014-08-281-2/+2
| | | | llvm-svn: 216660
* InstCombine: Remove redundant combinesDavid Majnemer2014-08-281-15/+0
| | | | | | | | InstSimplify already handles icmp (X+Y), X (and things like it) appropriately. The first thing that InstCombine does is run InstSimplify on the instruction. llvm-svn: 216659
* Fix: SLPVectorizer tried to move an instruction which was replaced by a ↵Erik Eckstein2014-08-281-4/+0
| | | | | | | | | | vector instruction. For a detailed description of the problem see the comment in the test file. The problematic moveBefore() calls are not required anymore because the new scheduling algorithm ensures a correct ordering anyway. llvm-svn: 216656
* Generate CMN when comparing a short int with minusDavid Xu2014-08-281-3/+41
| | | | llvm-svn: 216651
* Test commit. Fix whitespace from a previous patch of mine.Justin Hibbits2014-08-281-1/+1
| | | | llvm-svn: 216650
* [MCJIT] Fix format specifiers for debug output in RuntimeDyld.Lang Hames2014-08-282-3/+3
| | | | | | More work on http://llvm.org/PR20640 llvm-svn: 216648
* MC: Don't crash when the COFF section limit is reachedDavid Majnemer2014-08-281-6/+11
| | | | | | | I've decided not to commit a test, it takes 2.5 seconds to run on my an incredibly strong machine. llvm-svn: 216647
* [x86] Fix whitespace and formatting around this function withChandler Carruth2014-08-281-4/+5
| | | | | | clang-format, no functionality changed. llvm-svn: 216646
* [x86] Hoist conditions from *every single if* in this routine toChandler Carruth2014-08-281-12/+12
| | | | | | | | | | | a single early exit. And factor the subsequent cast<> from all but one block into a single variable. No functionality changed. llvm-svn: 216645
* [x86] Inline an SSE4 helper function for INSERT_VECTOR_ELT lowering, noChandler Carruth2014-08-281-58/+45
| | | | | | | | | | functionality changed. Separating this into two functions wasn't helping. There was a decent amount of boilerplate duplicated, and some subsequent refactorings here will pull even more common code out. llvm-svn: 216644
* InstSimplify: Move a transform from InstCombine to InstSimplifyDavid Majnemer2014-08-282-10/+35
| | | | | | | | Several combines involving icmp (shl C2, %X) C1 can be simplified without introducing any new instructions. Move them to InstSimplify; while we are at it, make them more powerful. llvm-svn: 216642
* [FastISel] Undo phi node updates when falling-back to SelectionDAG.Juergen Ributzka2014-08-281-4/+7
| | | | | | | | | | | | | | | | | | | | The included test case would fail, because the MI PHI node would have two operands from the same predecessor. This problem occurs when a switch instruction couldn't be selected. This happens always, because there is no default switch support for FastISel to begin with. The problem was that FastISel would first add the operand to the PHI nodes and then fall-back to SelectionDAG, which would then in turn add the same operands to the PHI nodes again. This fix removes these duplicate PHI node operands by reseting the PHINodesToUpdate to its original state before FastISel tried to select the instruction. This fixes <rdar://problem/18155224>. llvm-svn: 216640
* [FastISel]Juergen Ributzka2014-08-281-1/+8
| | | | | | | | | | | | | | | | | | | | Currently instructions are folded very aggressively for AArch64 into the memory operation, which can lead to the use of killed operands: %vreg1<def> = ADDXri %vreg0<kill>, 2 %vreg2<def> = LDRBBui %vreg0, 2 ... = ... %vreg1 ... This usually happens when the result is also used by another non-memory instruction in the same basic block, or any instruction in another basic block. This fix teaches hasTrivialKill to not only check the LLVM IR that the value has a single use, but also to check if the register that represents that value has already been used. This can happen when the instruction with the use was folded into another instruction (in this particular case a load instruction). This fixes rdar://problem/18142857. llvm-svn: 216634
* Revert "[FastISel][AArch64] Don't fold instructions too aggressively into ↵Juergen Ributzka2014-08-271-92/+16
| | | | | | | | the memory operation." Quentin pointed out that this is not the correct approach and there is a better and easier solution. llvm-svn: 216632
* Fix unaligned reads/writes in X86JIT and RuntimeDyldELF.Alexey Samsonov2014-08-272-49/+61
| | | | | | | | | | | | | | | | Summary: Introduce support::ulittleX_t::ref type to Support/Endian.h and use it in x86 JIT to enforce correct endianness and fix unaligned accesses. Test Plan: regression test suite Reviewers: lhames Subscribers: ributzka, llvm-commits Differential Revision: http://reviews.llvm.org/D5011 llvm-svn: 216631
* [FastISel][AArch64] Don't fold instructions too aggressively into the memory ↵Juergen Ributzka2014-08-271-16/+92
| | | | | | | | | | | | | | | | | | | | | operation. Currently instructions are folded very aggressively into the memory operation, which can lead to the use of killed operands: %vreg1<def> = ADDXri %vreg0<kill>, 2 %vreg2<def> = LDRBBui %vreg0, 2 ... = ... %vreg1 ... This usually happens when the result is also used by another non-memory instruction in the same basic block, or any instruction in another basic block. If the computed address is used by only memory operations in the same basic block, then it is safe to fold them. This is because all memory operations will fold the address computation and the original computation will never be emitted. This fixes rdar://problem/18142857. llvm-svn: 216629
* Use local variable in visitFADD. No functional change.Sanjay Patel2014-08-271-13/+11
| | | | llvm-svn: 216623
* [FastISel][AArch64] Fix a comment in my previous commit (r216617).Juergen Ributzka2014-08-271-1/+1
| | | | llvm-svn: 216622
* [FastISel][AArch64] Fix simplify address when the address comes from a shift.Juergen Ributzka2014-08-271-0/+4
| | | | | | | | | When the address comes directly from a shift instruction then the address computation cannot be folded into the memory instruction, because the zero register is not available as a base register. Simplify addess needs to emit the shift instruction and use the result as base register. llvm-svn: 216621
* Fix a double free in llvm::getBitcodeTargetTriple.Rafael Espindola2014-08-271-1/+1
| | | | | | Unfortunately this is only used by ld64, so no testcase, but should fix the darwin LTO bootstrap. llvm-svn: 216618
* [FastISel][AArch64] Use the zero register for stores.Juergen Ributzka2014-08-271-5/+19
| | | | | | | | | Use the zero register directly when possible to avoid an unnecessary register copy and a wasted register at -O0. This also uses integer stores to store a positive floating-point zero. This saves us from materializing the positive zero in a register and then storing it. llvm-svn: 216617
* Group unsafe-math optimizations for fsub into one block. No functional change.Sanjay Patel2014-08-271-14/+17
| | | | llvm-svn: 216616
* [FastISel] Fix a potential bug in FastEmitInst_riJuergen Ributzka2014-08-271-2/+1
| | | | | | | | FastEmitInst_ri was constraining the first operand without checking if it is a virtual register. Use constrainOperandRegClass as all the other FastEmitInst_* functions. llvm-svn: 216613
* Use local variable to improve readability. Sanjay Patel2014-08-271-15/+10
| | | | | | No functional change intended. llvm-svn: 216611
* typo in commentSanjay Patel2014-08-271-1/+1
| | | | llvm-svn: 216609
* X86 MC: Handle instructions like fxsave that match multiple operand sizesReid Kleckner2014-08-271-8/+18
| | | | | | | | | | | | | | | | Instructions like 'fxsave' and control flow instructions like 'jne' match any operand size. The loop I added to the Intel syntax matcher assumed that using a different size would give a different instruction. Now it handles the case where we get the same instruction for different memory operand sizes. This also allows us to remove the hack we had for unsized absolute memory operands, because we can successfully match things like 'jnz' without reporting ambiguity. Removing this hack uncovered test case involving 'fadd' that was ambiguous. The memory operand could have been single or double precision. llvm-svn: 216604
* InstCombine: Combine gep X, (Y-X) to YDavid Majnemer2014-08-271-14/+25
| | | | | | | | We try to perform this transform in InstSimplify but we aren't always able to. Sometimes, we need to insert a bitcast if X and Y don't have the same time. llvm-svn: 216598
* InstSimplify: Don't simplify gep X, (Y-X) to Y if types differDavid Majnemer2014-08-271-1/+2
| | | | | | | | | It's incorrect to perform this simplification if the types differ. A bitcast would need to be inserted for this to work. This fixes PR20771. llvm-svn: 216597
* Reland r216439 215441, majnemer has a real fix for PR20771.Nico Weber2014-08-271-11/+53
| | | | llvm-svn: 216586
* Return a std::unique_ptr when creating a new MemoryBuffer.Rafael Espindola2014-08-275-50/+43
| | | | llvm-svn: 216583
* Revert r216439 (and r216441, else the former doesn't revert cleanly).Nico Weber2014-08-271-53/+11
| | | | | | It caused PR 20771. I'll land a test on the clang side. llvm-svn: 216582
* Remove unused argument.Rafael Espindola2014-08-271-9/+6
| | | | llvm-svn: 216580
* Use BitVector instead of int in R600 SIISelLowering.Alexey Samsonov2014-08-271-3/+4
| | | | | | | int may not have enough bits in it, which was detected by UBSan bootstrap (it reported left shift by a too large constant). llvm-svn: 216579
* yaml::Stream doesn't need to take ownership of the buffer.Rafael Espindola2014-08-271-25/+26
| | | | | | In fact, most users were already using the StringRef version. llvm-svn: 216575
* InstSimplify: Compute comparison ranges for left shift instructionsDavid Majnemer2014-08-271-0/+16
| | | | | | | | 'shl nuw CI, x' produces [CI, CI << CLZ(CI)] 'shl nsw CI, x' produces [CI << CLO(CI)-1, CI] if CI is negative 'shl nsw CI, x' produces [CI, CI << CLZ(CI)-1] if CI is non-negative llvm-svn: 216570
* Revert "Limit the symbol search in DynamicLibrary to the module that was ↵Zachary Turner2014-08-271-9/+2
| | | | | | | | opened." This reverts commit r216563, which breaks lli's dynamic symbol resolution. llvm-svn: 216569
* [MCJIT] Replace a C-style cast in RuntimeDyldImpl.h.Lang Hames2014-08-271-1/+1
| | | | llvm-svn: 216568
* [MCJIT] More endianness fixes for RuntimeDyldMachO.Lang Hames2014-08-272-12/+28
| | | | | | http://llvm.org/PR20640 llvm-svn: 216567
* Limit the symbol search in DynamicLibrary to the module that was opened.Zachary Turner2014-08-271-2/+9
| | | | | | | | Differential Revision: http://reviews.llvm.org/D5030 Reviewed By: Reid Kleckner, Rafael Espindola llvm-svn: 216563
* Teach the AArch64 backend about v4f16 and v8f16Oliver Stannard2014-08-277-104/+425
| | | | | | | | This teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations. llvm-svn: 216555
* [SLP] Re-enable vectorization of GEP expressions (re-apply r210342 with a fix).Michael Zolotukhin2014-08-271-0/+101
| | | | llvm-svn: 216549
* Clang-format over X86AsmInstrumentation.* with LLVM style.Evgeniy Stepanov2014-08-272-129/+132
| | | | | | r216536 mistakenly used -style=Google instead of LLVM. llvm-svn: 216543
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