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* GVN-hoist: improve code generation for recursive GEPsSebastian Pop2016-07-271-42/+82
| | | | | | | | | | | | | | | | | | | When loading or storing in a field of a struct like "a.b.c", GVN is able to detect the equivalent expressions, and GVN-hoist would fail in the code generation. This is because the GEPs are not hoisted as scalar operations to avoid moving the GEPs too far from their ld/st instruction when the ld/st is not movable. So we end up having to generate code for the GEP of a ld/st when we move the ld/st. In the case of a GEP referring to another GEP as in "a.b.c" we need to code generate all the GEPs necessary to make all the operands available at the new location for the ld/st. With this patch we recursively walk through the GEP operands checking whether all operands are available, and in the case of a GEP operand, it recursively makes all its operands available. Code generation happens from the inner GEPs out until reaching the GEP that appears as an operand of the ld/st. Differential Revision: https://reviews.llvm.org/D22599 llvm-svn: 276841
* GVN-hoist: use DFS numbers instead of walking the instruction streamSebastian Pop2016-07-271-10/+3
| | | | | | | | | The patch replaces a function that walks the IR with a call to firstInBB() that uses the DFS numbering. NFC. Differential Revision: https://reviews.llvm.org/D22809 llvm-svn: 276840
* add a verbose mode to Loop->print() to print all the basic blocks of a loopSebastian Pop2016-07-271-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D22817 llvm-svn: 276838
* [ConstantFolding] Correctly handle failures in ↵David Majnemer2016-07-271-4/+13
| | | | | | | | | | | ConstantFoldConstantExpressionImpl Failures in ConstantFoldConstantExpressionImpl were ignored causing crashes down the line. This fixes PR28725. llvm-svn: 276827
* Reverting r276771 due to MSan failures.Andrew Kaylor2016-07-274-50/+0
| | | | llvm-svn: 276824
* AMDGPU: Use rcp for fdiv 1, x with fpmath metadataMatt Arsenault2016-07-261-1/+1
| | | | | | | Using rcp should be OK for safe math usually, so this should not be replacing the original fdiv. llvm-svn: 276823
* Revert r276136 "Use ValueOffsetPair to enhance value reuse during SCEV ↵Hans Wennborg2016-07-262-80/+33
| | | | | | | | | | expansion." It causes Clang tests to fail after Windows self-host (PR28705). (Also reverts follow-up r276139.) llvm-svn: 276822
* AMDGPU: Use implicit_def for selecting anyextMatt Arsenault2016-07-261-4/+7
| | | | llvm-svn: 276819
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-264-6/+14
| | | | | | | | | | | | | | | | | Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 llvm-svn: 276815
* AMDGPU/R600: Remove dead custom insertersMatt Arsenault2016-07-261-209/+1
| | | | | | The intrinsics for these were removed, so this is dead. llvm-svn: 276805
* AMDGPU: Minor AsmPrinter cleanupsMatt Arsenault2016-07-261-79/+84
| | | | llvm-svn: 276804
* [Hexagon] Post-increment loads/stores enhancementsKrzysztof Parzyszek2016-07-265-112/+99
| | | | | | | - Generate vector post-increment stores more aggressively. - Predicate post-increment and vector stores in early if-conversion. llvm-svn: 276800
* GlobalISel: add generic load and store instructions.Tim Northover2016-07-262-0/+71
| | | | | | | Pretty straightforward, the only oddity is the MachineMemOperand (which it's surprisingly difficult to share code for). llvm-svn: 276799
* [X86] Split out absdiff detection from SAD combine. NFC.Michael Kuperstein2016-07-261-59/+64
| | | | | | Preparation for supporting PSADBW emission for straight-line code. llvm-svn: 276798
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-13/+19
| | | | llvm-svn: 276793
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-263-5/+17
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-262-25/+85
| | | | | | | Change the bit simplifier to generate REG_SEQUENCE instructions in addition to COPY, which will handle cases of word insert/extract. llvm-svn: 276787
* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-262-10/+10
| | | | | | | | | | | | | | | | In an instruction like: CFI_INSTRUCTION .cfi_def_cfa ... we can drop the '.cfi_' prefix since that should be obvious by the context: CFI_INSTRUCTION def_cfa ... While being a terser and cleaner syntax this also prepares to dropping support for identifiers starting with a dot character so we can use it for expressions. Differential Revision: http://reviews.llvm.org/D22388 llvm-svn: 276785
* [MC] Don't crash when trying to emit a relocation against .bss.Davide Italiano2016-07-261-2/+2
| | | | | | Turn that into an error instead. llvm-svn: 276783
* [InstSimplify] Cast folding can be made more genericDavid Majnemer2016-07-261-46/+43
| | | | | | Use isEliminableCastPair to determine if a pair of casts are foldable. llvm-svn: 276777
* [LoopUtils] Sort headersAdam Nemet2016-07-261-3/+4
| | | | llvm-svn: 276776
* GlobalISel: add correct operand type to G_FRAME_INDEX instrs.Tim Northover2016-07-261-1/+1
| | | | | | Frame indices should use "addFrameIndex", not "addImm". llvm-svn: 276775
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-8/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* GlobalISel: omit braces on MachineInstr types when there's only one.Tim Northover2016-07-262-8/+15
| | | | | | Tidies up the representation a bit in the common case. llvm-svn: 276772
* Re-committing r275284: add support to inline __builtin_mempcpyAndrew Kaylor2016-07-264-0/+50
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 276771
* AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault2016-07-2610-56/+80
| | | | | | | | | ABIArgOffset is a problem because properly fsetting the KernArgSize requires that the reserved area before the real kernel arguments be correctly aligned, which requires fixing clover. llvm-svn: 276766
* AMDGPU: Add fp legacy instruction intrinsicsMatt Arsenault2016-07-265-2/+21
| | | | | | | This could use some additional optimization work to use mad/mac legacy. llvm-svn: 276764
* GlobalISel: add specialized buildCopy function to MachineInstrBuilder.Tim Northover2016-07-263-3/+7
| | | | | | NFC. llvm-svn: 276763
* GlobalISel: give MachineInstrBuilder a uniform interface. NFC.Tim Northover2016-07-262-50/+12
| | | | | | | | | | | Instead of an ad-hoc collection of "buildInstr" functions with varying numbers of registers, this uses variadic templates to provide for as many regs as needed! Also make IRtranslator use new "buildBr" function instead of some weird generic one that no-one else would really use. llvm-svn: 276762
* [mips] Fix typos in spelling of lowerRETURNADDR.Daniel Sanders2016-07-263-3/+3
| | | | | | The first letter was mistakenly capitalized. llvm-svn: 276753
* [Hexagon] Update store offset when not packetizing it with allocframeKrzysztof Parzyszek2016-07-262-15/+51
| | | | | | | | | | When the packetizer wants to put a store to a stack slot in the same packet with an allocframe, it updates the store offset to reflect the value of SP before it is updated by allocframe. If the store cannot be packetized with the allocframe after all, the offset needs to be updated back to the previous value. llvm-svn: 276749
* [ARM] Improve error messages for .arch_extension directiveOliver Stannard2016-07-261-4/+8
| | | | | | | | | | | | - More informative message when extension name is not an identifier token. - Stop parsing directive if extension is unknown (avoid duplicate error messages). - Report unsupported extensions with a source location, rather than report_fatal_error. Differential Revision: https://reviews.llvm.org/D22806 llvm-svn: 276748
* [ARM] Implement -mimplicit-it assembler optionOliver Stannard2016-07-263-38/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option, compatible with gas's -mimplicit-it, controls the generation/checking of implicit IT blocks in ARM/Thumb assembly. This option allows two behaviours that were not possible before: - When in ARM mode, emit a warning when assembling a conditional instruction that is not in an IT block. This is enabled with -mimplicit-it=never and -mimplicit-it=thumb. - When in Thumb mode, automatically generate IT instructions when an instruction with a condition code appears outside of an IT block. This is enabled with -mimplicit-it=thumb and -mimplicit-it=always. The default option is -mimplicit-it=arm, which matches the existing behaviour (allow conditional ARM instructions outside IT blocks without warning, and error if a conditional Thumb instruction is outside an IT block). The general strategy for generating IT blocks in Thumb mode is to keep a small list of instructions which should be in the IT block, and only emit them when we encounter something in the input which means we cannot continue the block. This could be caused by: - A non-predicable instruction - An instruction with a condition not compatible with the IT block - The IT block already contains 4 instructions - A branch-like instruction (including ALU instructions with the PC as the destination), which cannot appear in the middle of an IT block - A label (branching into an IT block is not legal) - A change of section, architecture, ISA, etc - The end of the assembly file. Some of these, such as change of section and end of file, are parsed outside of the ARM asm parser, so I've added a new virtual function to AsmParser to ensure any previously-parsed instructions have been emitted. The ARM implementation of this flushes the currently pending IT block. We now have to try instruction matching up to 3 times, because we cannot know if the current IT block is valid before matching, and instruction matching changes depending on the IT block state (due to the 16-bit ALU instructions, which set the flags iff not in an IT block). In the common case of not having an open implicit IT block and the instruction being matched not needing one, we still only have to run the matcher once. I've removed the ITState.FirstCond variable, because it does not store any information that isn't already represented by CurPosition. I've also updated the comment on CurPosition to accurately describe it's meaning (which this patch doesn't change). Differential Revision: https://reviews.llvm.org/D22760 llvm-svn: 276747
* [X86][SSE] Fixed issue with memory folding of (v)cvtsd2ss intrinsicsSimon Pilgrim2016-07-261-2/+2
| | | | | | | | Fixed typo in the intrinsic definitions of (v)cvtsd2ss with memory folding. This was only unearthed when rL276102 started using the intrinsic again..... llvm-svn: 276740
* [mips] MIPS64R6 compact branch supportSimon Dardis2016-07-265-11/+98
| | | | | | | | | | | | | MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
* Fixed spelling in commentSimon Pilgrim2016-07-261-1/+1
| | | | llvm-svn: 276738
* [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliasesSimon Dardis2016-07-264-5/+40
| | | | | | | | | | | Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
* [X86] Remove isCommutable=1 from instructions that also load. Commuting such ↵Craig Topper2016-07-262-9/+13
| | | | | | instruction isn't useful as it would unfold the load. The exception being FMA3 instructions. llvm-svn: 276733
* [AVX512] Don't mark ADDSSZr_Int or MULSSZr_Int as commutable. The intrinsics ↵Craig Topper2016-07-261-2/+2
| | | | | | have one of their arguments indicated as passing through the high bits and we can't commute that. llvm-svn: 276732
* Reapply: [InstSimplify] Add support for bitcasts"David Majnemer2016-07-261-0/+29
| | | | | | | This reverts commit r276700 and reapplies r276698. The relevant clang tests have been updated. llvm-svn: 276727
* LiveIntervalAnalysis: Fix handleMoveDown() problemMatthias Braun2016-07-261-0/+2
| | | | | | | | | | | | If we move a last-use register read to a later position we may skip intermediate segments. This may require us to not only extend the segment before the NewIdx, but also extend the segment live-in to OldIdx. This switches LiveIntervalTest to use AMDGPU so we can test subregister liveness. llvm-svn: 276724
* GlobalISel: remove redundant ';'s. NFCTim Northover2016-07-263-3/+3
| | | | llvm-svn: 276723
* GVN-hoist: use a DFS numbering of instructions (PR28670)Sebastian Pop2016-07-261-31/+26
| | | | | | | | | | | Instead of DFS numbering basic blocks we now DFS number instructions that avoids the costly operation of which instruction comes first in a basic block. Patch mostly written by Daniel Berlin. Differential Revision: https://reviews.llvm.org/D22777 llvm-svn: 276714
* GVN-hoist: limit hoisting depth (PR28670)Sebastian Pop2016-07-261-0/+11
| | | | | | | | | | This patch adds an option to specify the maximum depth in a BB at which to consider hoisting instructions. Hoisting instructions from a deeper level is not profitable as it increases register pressure and compilation time. Differential Revision: https://reviews.llvm.org/D22772 llvm-svn: 276713
* [safestack] Fix stack guard live range.Evgeniy Stepanov2016-07-262-2/+4
| | | | | | Stack guard slot is live throughout the function. llvm-svn: 276712
* [ARM] Saturation instructions are DSP-onlyRenato Golin2016-07-253-9/+16
| | | | | | | | | | | The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
* Revert "[InstSimplify] Add support for bitcasts"David Majnemer2016-07-251-29/+0
| | | | | | | This reverts commit r276698. Clang has tests which rely on the optimizer :( llvm-svn: 276700
* [InstSimplify] Add support for bitcastsDavid Majnemer2016-07-251-0/+29
| | | | | | | BitCasts of BitCasts can be folded away as can BitCasts which don't change the type of the operand. llvm-svn: 276698
* [WebAssembly] Update for Target API (TargetRegistry::RegisterMCAsmBackend) ↵David Blaikie2016-07-251-1/+2
| | | | | | change llvm-svn: 276694
* GlobalISel: add generic casts to IRTranslatorTim Northover2016-07-253-1/+38
| | | | | | | | | This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
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