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* [PowerPC] Minor correction to r226432Hal Finkel2015-01-191-2/+1
| | | | | | | | | | We don't need to exclude patchpoints from the implicit r2 dependence in FastISel because it is added as an implicit operand and, thus, should not confuse that StackMap code. By inspection / no test case. llvm-svn: 226434
* [MIScheduler] Slightly better handling of constrainLocalCopy when both ↵Michael Kuperstein2015-01-191-4/+7
| | | | | | | | | | source and dest are local This fixes PR21792. Differential Revision: http://reviews.llvm.org/D6823 llvm-svn: 226433
* [PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2Hal Finkel2015-01-192-5/+18
| | | | | | | | | | | Our PPC64 ELF V2 call lowering logic added r2 as an operand to all direct call instructions in order to represent the dependency on the TOC base pointer value. Restricting this to ELF V2, however, does not seem to make sense: calls under ELF V1 have the same dependence, and indirect calls have an r2 dependence just as direct ones. Make sure the dependence is noted for all calls under both ELF V1 and ELF V2. llvm-svn: 226432
* [x86] Change AVX512 intrinsics to take a 8-bit immediate for the comparision ↵Craig Topper2015-01-193-8/+41
| | | | | | kind instead of a 32-bit immediate. This better aligns with the emitted instruction. It also matches SSE and AVX1 equivalents. Also add auto upgrade support. llvm-svn: 226430
* [PM] Lift the analyses into the interface forChandler Carruth2015-01-196-18/+14
| | | | | | | | | | SplitLandingPadPredecessors and remove the Pass argument from its interface. Another step to the utilities being usable with both old and new pass managers. llvm-svn: 226426
* unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizerDavid Blaikie2015-01-183-14/+10
| | | | llvm-svn: 226416
* std::unique_ptrify the MCStreamer argument to createAsmPrinterDavid Blaikie2015-01-1817-61/+76
| | | | llvm-svn: 226414
* [PowerPC] Don't hard-code R2 as register when processing TOC relocationsHal Finkel2015-01-181-3/+3
| | | | | | | | | | | Instructions that have high-order TOC relocations always carry R2 as their base register, so it does not matter whether we take the register from the instruction or just hard-code it in PPCAsmPrinter. In the future, however, we might want to apply these relocations to instructions using a different register, so taking the register from the instruction is a better thing to do. No change in functionality here, however. llvm-svn: 226403
* [PowerPC] Add some FIXMEs for fastcc and FPR <-> GPR movesHal Finkel2015-01-181-0/+6
| | | | | | | So we don't forget, once we support FPR <-> GPR moves on the P8, we'll likely want to re-visit this part of the calling convention. llvm-svn: 226401
* [PowerPC] Initial PPC64 calling-convention changes for fastccHal Finkel2015-01-182-63/+161
| | | | | | | | | | | | | | | | | The default calling convention specified by the PPC64 ELF (V1 and V2) ABI is designed to work with both prototyped and non-prototyped/varargs functions. As a result, GPRs and stack space are allocated for every argument, even those that are passed in floating-point or vector registers. GlobalOpt::OptimizeFunctions will transform local non-varargs functions (that do not have their address taken) to use the 'fast' calling convention. When functions are using the 'fast' calling convention, don't allocate GPRs for arguments passed in other types of registers, and don't allocate stack space for arguments passed in registers. Other changes for the fast calling convention may be added in the future. llvm-svn: 226399
* [PM] Pull the analyses used for another utility routine into its APIChandler Carruth2015-01-186-63/+98
| | | | | | | | | | | rather than relying on the pass object. This one is a bit annoying, but will pay off. First, supporting this one will make the next one much easier, and for utilities like LoopSimplify, this is moving them (slowly) closer to not having to pass the pass object around throughout their APIs. llvm-svn: 226396
* [PM] Sink the specific analyses preserved by SplitBlock into itsChandler Carruth2015-01-184-18/+24
| | | | | | | | | interface, removing Pass from its interface. This also makes those analyses optional so that passes which don't even preserve these (or use them) can skip the logic entirely. llvm-svn: 226394
* [PM] Replace another Pass argument with specific analyses that areChandler Carruth2015-01-183-27/+22
| | | | | | | | | optionally updated by MergeBlockIntoPredecessors. No functionality changed, just refactoring to clear the way for the new pass manager. llvm-svn: 226392
* [PM] Refactor how the LoopRotation pass access the DominatorTree.Chandler Carruth2015-01-181-20/+18
| | | | | | | | Instead of querying the pass every where we need to, do that once and cache a pointer in the pass object. This is both simpler and I'm about to add yet another place where we need to dig out that pointer. llvm-svn: 226391
* [PM] Lift the actual analyses used into the inferface rather thanChandler Carruth2015-01-181-10/+7
| | | | | | | | | | | | accepting a Pass and querying it for analyses. This is necessary to allow the utilities to work both with the old and new pass managers, and I also think this makes the interface much more clear and helps the reader know what analyses the utility can actually handle. I plan to repeat this process iteratively to clean up all the pass utilities. llvm-svn: 226386
* [PM] Now that LoopInfo isn't in the Pass type hierarchy, it is muchChandler Carruth2015-01-189-54/+38
| | | | | | | | | | | | cleaner to derive from the generic base. Thise removes a ton of boiler plate code and somewhat strange and pointless indirections. It also remove a bunch of the previously needed friend declarations. To fully remove these, I also lifted the verify logic into the generic LoopInfoBase, which seems good anyways -- it is generic and useful logic even for the machine side. llvm-svn: 226385
* [PM] Cleanup more warnings my refactoring exposed where now we haveChandler Carruth2015-01-171-0/+2
| | | | | | | | | unused variables in a no-asserts build. I've fixed this by putting the entire loop behind an #ifndef as it contains nothing other than asserts. llvm-svn: 226377
* [PM] Remove a dead field.Chandler Carruth2015-01-171-7/+3
| | | | | | | | | This was dead even before I refactored how we initialized it, but my refactoring made it trivially dead and it is now caught by a Clang warning. This fixes the warning and should clean up the -Werror bot failures (sorry!). llvm-svn: 226376
* [PM] Split the LoopInfo object apart from the legacy pass, creatingChandler Carruth2015-01-1734-137/+146
| | | | | | | | | | a LoopInfoWrapperPass to wire the object up to the legacy pass manager. This switches all the clients of LoopInfo over and paves the way to port LoopInfo to the new pass manager. No functionality change is intended with this iteration. llvm-svn: 226373
* [PowerPC] Don't list R11 as a patchpoint scratch registerHal Finkel2015-01-171-9/+1
| | | | | | | | | | R11's status is the same under both the PPC64 ELF V1 and V2 ABIs: it is reserved for use as an "environment pointer" for compilation models that require such a thing. We don't, we also don't need a second scratch register, and because we support only "local" patchpoint call targets, we might as well let R11 be used for anyregcc patchpoints. llvm-svn: 226369
* Improve DAG combine pass on certain IR vector patternsMehdi Amini2015-01-171-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector produced suboptimal code in AVX2 mode with certain IR combinations. In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32 (undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical, but then mysteriously generated rather bad code; the movq/movhpd combination didn't match. The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs would get promoted to 4f32 by the type legalizer, eventually resulting in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing these were both half the output size, concatted them and then produced a shuffle. However, the resulting concat + shuffle was more complex than it should be; in the case where the upper half of the output is undef, we probably want to generate shuffle + concat instead. This enhancement causes the vector_shuffle combine step to recognize this suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR in case the same suboptimal pattern occurs for other reasons. This results in the optimizer correctly producing the optimal movq + movhpd sequence for all three variations on this IR, even with AVX2. I've included a test case. Radar link: rdar://problem/19287012 Fix for PR 21943. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 226360
* [RuntimeDyld] Tidy up emitCommonSymbols a little. NFC.Lang Hames2015-01-172-46/+61
| | | | llvm-svn: 226358
* Remove std::move that was preventing return value optimization.Richard Trieu2015-01-172-4/+4
| | | | llvm-svn: 226356
* RegisterCoalescer: Cleanup and improved comment for a subtle detail.Matthias Braun2015-01-171-6/+8
| | | | llvm-svn: 226353
* RegisterCoalescer: Cleanup by factoring out a common expressionMatthias Braun2015-01-171-5/+6
| | | | llvm-svn: 226352
* RegisterCoalescer: Cleanup comment styleMatthias Braun2015-01-171-190/+174
| | | | | | | | | | | - Consistenly put comments above the function declaration, not the definition. To achieve this some duplicate comments got merged and some comment parts describing implementation details got moved into their functions. - Consistently use doxygen comments above functions. - Do not use doxygen comments inside functions. llvm-svn: 226351
* RegisterCoalescer: Drive-by typo + whitespace fixMatthias Braun2015-01-171-2/+2
| | | | llvm-svn: 226350
* [RuntimeDyld] Remove the brace initialization that was introduced in r226341.Lang Hames2015-01-171-2/+2
| | | | | | Evidently MSVC doesn't like it. llvm-svn: 226349
* Update a commentPhilip Reames2015-01-161-1/+3
| | | | | | Be a bit more explicit about the fact that addrspace(1) is not reserved. llvm-svn: 226344
* clang-format all the GC related files (NFC)Philip Reames2015-01-1610-295/+290
| | | | | | Nothing interesting here... llvm-svn: 226342
* [RuntimeDyld] Track symbol visibility in RuntimeDyld.Lang Hames2015-01-165-38/+89
| | | | | | | | | | | | | | | | | | | RuntimeDyld symbol info previously consisted of just a Section/Offset pair. This patch replaces that pair type with a SymbolInfo class that also tracks symbol visibility. A new method, RuntimeDyld::getExportedSymbolLoadAddress, is introduced which only returns a non-zero result for exported symbols. For non-exported or non-existant symbols this method will return zero. The RuntimeDyld::getSymbolAddress method retains its current behavior, returning non-zero results for all symbols regardless of visibility. No in-tree clients of RuntimeDyld are changed. The newly introduced functionality will be used by the Orc APIs. No test case: Since this patch doesn't modify the behavior for any in-tree clients we don't have a good tool to test this with yet. Once Orc is in we can use it to write regression tests that test these changes. llvm-svn: 226341
* Fix the Archive::Child::getRawSize() method used by llvm-objdump’s ↵Kevin Enderby2015-01-161-1/+1
| | | | | | | | -archive-headers option and tweak its use in llvm-objdump. Add back the test case for the -archive-headers option. llvm-svn: 226332
* [Hexagon] Converting halfword to doubleword multiply intrinsics.Colin LeMahieu2015-01-161-37/+33
| | | | llvm-svn: 226326
* [Hexagon] Converting accumulating halfword multiply intrinsics to patterns.Colin LeMahieu2015-01-161-90/+65
| | | | llvm-svn: 226324
* [Hexagon] Beginning converting intrinsics to patterns instead of duplicated ↵Colin LeMahieu2015-01-161-71/+54
| | | | | | definitions. Converting halfword multiply intrinsics. llvm-svn: 226318
* [Hexagon] Fix 226309, replacement atomic store patterns didn't actually ↵Colin LeMahieu2015-01-161-0/+17
| | | | | | exist, added new versions. llvm-svn: 226315
* X86: fix comment typo in AsmParserSaleem Abdulrasool2015-01-161-1/+1
| | | | | | Fix a typo. NFC. llvm-svn: 226313
* Move ownership of GCStrategy objects to LLVMContextPhilip Reames2015-01-1616-35/+64
| | | | | | | | | | | | Note: This change ended up being slightly more controversial than expected. Chandler has tentatively okayed this for the moment, but I may be revisiting this in the near future after we settle some high level questions. Rather than have the GCStrategy object owned by the GCModuleInfo - which is an immutable analysis pass used mainly by gc.root - have it be owned by the LLVMContext. This simplifies the ownership logic (i.e. can you have two instances of the same strategy at once?), but more importantly, allows us to access the GCStrategy in the middle end optimizer. To this end, I add an accessor through Function which becomes the canonical way to get at a GCStrategy instance. In the near future, this will allows me to move some of the checks from http://reviews.llvm.org/D6808 into the Verifier itself, and to introduce optimization legality predicates for some of the recent additions to InstCombine. (These will follow as separate changes.) Differential Revision: http://reviews.llvm.org/D6811 llvm-svn: 226311
* [Hexagon] Removing old duplicate atomic load/store patterns.Colin LeMahieu2015-01-161-65/+0
| | | | llvm-svn: 226309
* Remove gc.root's findCustomSafePoints mechanismPhilip Reames2015-01-164-43/+10
| | | | | | | | | | | | Searching all of the existing gc.root implementations I'm aware of (all three of them), there was exactly one use of this mechanism, and that was to implement a performance improvement that should have been applied to the default lowering. Having this function is requiring a dependency on a CodeGen class (MachineFunction), in a class which is otherwise completely independent of CodeGen. I could solve this differently, but given that I see absolutely no value in preserving this mechanism, I going to just get rid of it. Note: Tis is the first time I'm intentionally breaking previously supported gc.root functionality. Given 3.6 has branched, I believe this is a good time to do this. Differential Revision: http://reviews.llvm.org/D7004 llvm-svn: 226305
* [Hexagon] Converting old patterns to new versions using classes.Colin LeMahieu2015-01-161-164/+253
| | | | llvm-svn: 226304
* [AVX512] Add intrinsics for masked aligned FP loads and storesAdam Nemet2015-01-161-0/+25
| | | | | | | | | | Similar to the unaligned cases. Test was generated with update_llc_test_checks.py. Part of <rdar://problem/17688758> llvm-svn: 226296
* IR: Allow 16-bits for column infoDuncan P. N. Exon Smith2015-01-162-4/+4
| | | | | | Raise the limit for column information from 8 bits to 16 bits. llvm-svn: 226291
* IR: Cleanup dead code, NFCDuncan P. N. Exon Smith2015-01-161-5/+0
| | | | | | | Line/column fixups already exist in `MDLocation`. Delete the duplicated logic in `DebugLoc`. llvm-svn: 226290
* [Hexagon] Updating call/jump instruction patterns.Colin LeMahieu2015-01-165-45/+40
| | | | llvm-svn: 226288
* [X86][DAG] Disable target specific combine on INSERTPS dag nodes at -O0.Andrea Di Biagio2015-01-161-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables target specific combine on X86ISD::INSERTPS dag nodes if optlevel is CodeGenOpt::None. The backend currently implements a target specific combine rule that converts a vector load used by an INSERTPS dag node into a scalar load plus a scalar_to_vector. This allows ISel to select a single INSERTPSrm instead of two instructions (i.e. a vector load plus INSERTPSrr). However, the existing target combine rule on INSERTPS nodes only works under the assumption that ISel will always be able to match an INSERTPSrm. This is not true in general at -O0, since the backend only allows folding a load into the memory operand of an instruction if the optimization level is not CodeGenOpt::None. In the example below: // __m128 test(__m128 a, __m128 *b) { __m128 c = _mm_insert_ps(a, *b, 1 << 6); return c; } // Before this patch, at -O0, the backend would have canonicalized the load to 'b' into a scalar load plus scalar_to_vector. Later on, ISel would have selected an INSERTPSrr leaving the insertps mask in an inconsistent state: movss 4(%rdi), %xmm1 insertps $64, %xmm1, %xmm0 # xmm0 = xmm1[1],xmm0[1,2,3]. With this patch, the backend avoids folding the vector load into the operand of the INSERTPS. The new codegen at -O0 is: movaps (%rdi), %xmm1 insertps $64, %xmm1, %xmm0 # %xmm1[1],xmm0[1,2,3]. llvm-svn: 226277
* [mips] Remove a redundant semicolon and add space before curly brackets. NFC.Toma Tabacu2015-01-161-2/+2
| | | | llvm-svn: 226269
* Revert r226242 - Revert Revert Don't create new comdats in CodeGenTimur Iskhodzhanov2015-01-164-52/+35
| | | | | | This breaks AddressSanitizer (ninja check-asan) on Windows llvm-svn: 226251
* [PowerPC] Adjust PatchPoints for ppc64leHal Finkel2015-01-161-1/+9
| | | | | | | | | | Bill Schmidt pointed out that some adjustments would be needed to properly support powerpc64le (using the ELF V2 ABI). For one thing, R11 is not available as a scratch register, so we need to use R12. R12 is also available under ELF V1, so to maintain consistency, I flipped the order to make R12 the first scratch register in the array under both ABIs. llvm-svn: 226247
* Fix Reassociate handling of constant in presence of undef floatMehdi Amini2015-01-161-3/+6
| | | | | | http://reviews.llvm.org/D6993 llvm-svn: 226245
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