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* [AMDGPU] fcaninicalize optimization for GFX9+Stanislav Mekhanoshin2017-07-132-8/+23
| | | | | | | | | | | | | | Since GFX9 supports denorm modes for v_min_f32/v_max_f32 that is possible to further optimize fcanonicalize and remove it if applied to min/max given their operands are known not to be an sNaN or that sNaNs are not supported. Additionally we can remove fcanonicalize if denorms are supported for the VT and we know that its argument is never a NaN. Differential Revision: https://reviews.llvm.org/D35335 llvm-svn: 307976
* [DWARF] Introduce verification for the unit header chain in .debug_info ↵Spyridoula Gravani2017-07-132-0/+94
| | | | | | | | | | | | | | | section to llvm-dwarfdump. This patch adds verification checks for the unit header chain in the .debug_info section. Specifically, for each unit in the .debug_info section, the verifier checks that: The unit length is valid (i.e. the unit can actually fit in the .debug_info section) The dwarf version of the unit is valid The address size is valid (4 or 8) The unit type (if the unit is in dwarf5) is valid The debug_abbrev_offset is valid llvm-svn: 307975
* [libFuzzer] move code around; NFCKostya Serebryany2017-07-132-69/+60
| | | | llvm-svn: 307973
* AMDGPU: Annotate call graph with used featuresMatt Arsenault2017-07-132-68/+144
| | | | | | | Previously this wouldn't detect used features indirectly used in callee functions. llvm-svn: 307967
* [Dominators] Simplify templatesJakub Kuderski2017-07-131-16/+6
| | | | | | | | | | | | | | Summary: DominatorTreeBase and related classes used overcomplicated template machinery. This patch simplifies them and gets rid of DominatorTreeBaseTraits and DominatorTreeBaseByTraits, which weren't actually used outside the DomTree construction. Reviewers: dberlin, sanjoy, davide, grosser Reviewed By: dberlin, davide, grosser Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35285 llvm-svn: 307953
* [NFC] Move DEBUG_TYPE below includes in HexagonJakub Kuderski2017-07-137-14/+14
| | | | llvm-svn: 307947
* [PDB] Fix type server handling for archivesReid Kleckner2017-07-133-16/+13
| | | | | | | | | | | | | | | | | | | Summary: This fixes type indices for SDK or CRT static archives. Previously we'd try to look next to the archive object file path, which would not exist on the local machine. Also error out if we can't resolve a type server record. Hypothetically we can recover from this error by discarding debug info for this object, but that is not yet implemented. Reviewers: ruiu, amccarth Subscribers: aprantl, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D35369 llvm-svn: 307946
* [NFC] Move DEBUG_TYPE macro below includes...Jakub Kuderski2017-07-131-2/+2
| | | | | | in MachineCombiner.cpp. llvm-svn: 307940
* Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-07-136-372/+0
| | | | | | | This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939
* [Hexagon] Use VSPLAT instead of COMBINE for vectors of type v2i32, NFCKrzysztof Parzyszek2017-07-132-29/+28
| | | | | | This cleans up the vector shift patterns. llvm-svn: 307935
* [PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16Nemanja Ivanovic2017-07-137-67/+126
| | | | | | | | | | | | | As outlined in the PR, we didn't ensure that displacements for DQ-Form instructions are multiples of 16. Since the instruction encoding encodes a quad-word displacement, a sub-16 byte displacement is meaningless and ends up being encoded incorrectly. Fixes https://bugs.llvm.org/show_bug.cgi?id=33671. Differential Revision: https://reviews.llvm.org/D35007 llvm-svn: 307934
* Fix unused variable warning on EXPENSIVE_CHECKS release builds. NFCI.Simon Pilgrim2017-07-131-1/+1
| | | | llvm-svn: 307929
* [AArch64] Implement support for windows style vararg functionsMartin Storsjo2017-07-135-8/+57
| | | | | | | | | | | Pass parameters properly in calls to such functions (pass all floats in integer registers), and handle va_start properly (allocate stack immediately below the arguments on the stack, to save the register arguments into a single continuous array). Differential Revision: https://reviews.llvm.org/D35006 llvm-svn: 307928
* Put std::mutex usage behind #ifdefs to pacify the sanitizer buildbotReid Kleckner2017-07-131-0/+22
| | | | llvm-svn: 307925
* Support: Add llvm::center_justify.Frederich Munch2017-07-131-6/+23
| | | | | | | | | | | | | | Summary: Completes the set. Reviewers: ruiu Reviewed By: ruiu Subscribers: ruiu, llvm-commits Differential Revision: https://reviews.llvm.org/D35278 llvm-svn: 307922
* Reapply [GlobalOpt] Remove unreachable blocks before optimizing a function.Davide Italiano2017-07-131-0/+18
| | | | | | | This commit reapplies r307215 now that we found out and fixed the cause of the cfi test failure (in r307871). llvm-svn: 307920
* [AArch64] Enable the mnemonic spell checkerSjoerd Meijer2017-07-131-7/+14
| | | | | | | | | The AsmParser mnemonic spell checker was introduced in r307148 and enabled only for ARM. This patch enables it for AArch64. Differential Revision: https://reviews.llvm.org/D35357 llvm-svn: 307918
* [AArch64] Add an SVE target feature to the backend and TargetParser.Amara Emerson2017-07-134-0/+9
| | | | | | | The feature will be used properly once assembler/disassembler support begins to land. llvm-svn: 307917
* [AArch64] Add preliminary support for ARMv8.1 SUB/AND atomicsMatthew Simpson2017-07-133-3/+14
| | | | | | | This patch is a follow-up to r305893 and adds preliminary support for the fetch_sub and fetch_and operations. llvm-svn: 307913
* [RuntimeUnrolling] Update DomTree correctly when exit blocks have successorsAnna Thomas2017-07-131-2/+28
| | | | | | | | | | | | | | | | Summary: When we runtime unroll with multiple exit blocks, we also need to update the immediate dominators of the immediate successors of the exit blocks. Reviewers: reames, mkuper, mzolotukhin, apilipenko Reviewed by: mzolotukhin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35304 llvm-svn: 307909
* Reland "[mips] Fix multiprecision arithmetic."Simon Dardis2017-07-135-230/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
* [ARM] GlobalISel: Support G_BRDiana Picus2017-07-131-0/+3
| | | | | | | | This boils down to not crashing in reg bank select due to the lack of register operands on this instruction, and adding some tests. The instruction selection is already covered by the TableGen'erated code. llvm-svn: 307904
* [PM] Use range-based for loops in LegacyPassManager.cpp (NFC).Florian Hahn2017-07-131-28/+23
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch replaces a bunch of iterator-based for loops with range-based for loops. There are 2 iterator-based loops left in this file in removeNotPreservedAnalysis, but I think those cannot be replaced by range-based for loops as they modify the container they are iterating over. Unless I missed something, this schould be a NFC and I would appreciate if someone could have a quick look to confirm that. Reviewers: chandlerc, pcc, jhenderson Reviewed By: jhenderson Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D35310 llvm-svn: 307902
* [DAGCombiner] Fix issue with rotate combines asserting if the constant value ↵Simon Pilgrim2017-07-131-15/+18
| | | | | | types differ from the result type. llvm-svn: 307900
* [ARM] Tidy up and organise better ARM.td. NFC.Javed Absar2017-07-131-183/+248
| | | | | | | | | | | This patch tidies up and organises ARM.td so that it is easier to understandand and extend in the future. Reviewed by: @hahn, @rovka Differential Revision: https://reviews.llvm.org/D35248 llvm-svn: 307897
* Fixup r307893: Silence warningDiana Picus2017-07-131-0/+2
| | | | | | | Silence unused variable warning in release builds. *sigh* llvm-svn: 307896
* Use isNullConstantOrNullSplatConstant helper. NFCI.Simon Pilgrim2017-07-131-3/+2
| | | | llvm-svn: 307895
* Fix whitespace indentation. NFCI.Simon Pilgrim2017-07-131-2/+2
| | | | llvm-svn: 307894
* [ARM] GlobalISel: Move local variable. NFCDiana Picus2017-07-131-4/+10
| | | | | | | Move a local variable from outside a switch to inside every case that needs it (which isn't all of the cases, of course). llvm-svn: 307893
* [AVR] Fix broken indentationDylan McKay2017-07-131-1/+1
| | | | llvm-svn: 307891
* [AVR] Add a 'LLVM_FALLTHROUGH' statement to the AsmParserDylan McKay2017-07-131-0/+1
| | | | | | Should fix warnings in the build. llvm-svn: 307890
* [ARM] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-07-132-0/+54
| | | | | | | | | | | | | | | | | | | Summary: Similar to X86, it should be safe to inline callees if their target-features are a subset of the caller. As some subtarget features provide different instructions depending on whether they are set or unset (e.g. ThumbMode and ModeSoftFloat), we use a whitelist of target-features describing hardware capabilities only. Reviewers: kristof.beyls, rengolin, t.p.northover, SjoerdMeijer, peter.smith, silviu.baranga, efriedma Reviewed By: SjoerdMeijer, efriedma Subscribers: dschuff, efriedma, aemerson, sdardis, javed.absar, arichardson, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34697 llvm-svn: 307889
* [AVR] Fix indirect calls to function pointersDylan McKay2017-07-131-2/+14
| | | | | | Patch by Carl Peto. llvm-svn: 307888
* fix typos in comments and error messges; NFCHiroshi Inoue2017-07-133-4/+4
| | | | llvm-svn: 307885
* [X86] Simplify the getHostCPUName for AMD family 6 and 15.Craig Topper2017-07-131-38/+11
| | | | | | As far as I can tell we can simply distinguish based on features rather than model number. Many of the strings we were previously using are treated the same by the backend. llvm-svn: 307884
* [TargetLowering] Add hook for adding target MMO flags when doing ISel.Geoff Berry2017-07-131-0/+2
| | | | | | | | | | | | | Summary: Add TargetLowering hook getMMOFlags() to add target specific MMO flags to load/store instructions created by ISel. Reviewers: bogner, hfinkel, qcolombet, MatzeB Subscribers: mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34962 llvm-svn: 307879
* [MIR] Add support for printing and parsing target MMO flagsGeoff Berry2017-07-136-6/+81
| | | | | | | | | | | | | | | | | Summary: Add target hooks for printing and parsing target MMO flags. Targets may override getSerializableMachineMemOperandTargetFlags() to return a mapping from string to flag value for target MMO values that should be serialized/parsed in MIR output. Add implementation of this hook for AArch64 SuppressPair MMO flag. Reviewers: bogner, hfinkel, qcolombet, MatzeB Subscribers: mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34962 llvm-svn: 307877
* [libFuzzer] make sure that -reduce_inputs=1 deletes redundant files in the ↵Kostya Serebryany2017-07-132-3/+21
| | | | | | corpus llvm-svn: 307875
* [libFuzzer] experimental feature -reduce_inputs (off by default) that tries ↵Kostya Serebryany2017-07-139-16/+102
| | | | | | to replace elements in the corpus with smaller ones that have the same feature set. Still needs tuning llvm-svn: 307873
* [DWARF] Fixing a bug with processing of DWARF v5 indexed strings in Mach-O ↵Wolfgang Pieb2017-07-131-4/+4
| | | | | | | | | | | objects. Code to convert MachO - specific section debug section names to standard DWARF v5 section names was in the wrong place. Differential Revision: https://reviews.llvm.org/D35321 llvm-svn: 307872
* [CodeGenPrepare] Don't create dead instructions in addrmode sinkingEli Friedman2017-07-121-12/+18
| | | | | | | | | | When we fail to sink an instruction, we must make sure not to modify the function; otherwise, we end up in an infinite loop because CodeGenPrepare iterates until it doesn't make any changes. Fixes https://bugs.llvm.org/show_bug.cgi?id=33608 . llvm-svn: 307866
* [PGO] Enhance pgo counter promotionXinliang David Li2017-07-121-42/+115
| | | | | | | | | | | | | | | | | | | | | | | This is an incremental change to the promotion feature. There are two problems with the current behavior: 1) loops with multiple exiting blocks are totally disabled 2) a counter update can only be promoted one level up in the loop nest -- which does help much for short trip count inner loops inside a high trip-count outer loops. Due to this limitation, we still saw very large profile count fluctuations from run to run for the affected loops which are usually very hot. This patch adds the support for promotion counters iteratively across the loop nest. It also turns on the promotion for loops with multiple exiting blocks (with a limit). For single-threaded applications, the performance impact is flat on average. For instance, dealII improves, but povray regresses. llvm-svn: 307863
* [libFuzzer] relax test/shrink.test a bit (got broken on windows)Kostya Serebryany2017-07-121-1/+1
| | | | llvm-svn: 307862
* AMDGPU: Fix converting unanalyzable global loads to SMRDMatt Arsenault2017-07-121-4/+5
| | | | | | | Not all memory dependence queries succeed, so this needs to be conservative if it fails. llvm-svn: 307861
* [SjLj] Replace recursive block marking algorithm with iterative algorithmGerolf Hoflehner2017-07-121-2/+5
| | | | | | | | | | | | | | | | Summary: Some programs run into a stack overflow issue. This change avoids this problem by replacing the recursive algorithm with the iterative version. Reviewers: MatzeB, t.p.northover, dblaikie Reviewed By: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35105 llvm-svn: 307860
* [libFuzzer] remove include <sanitizer/coverage_interface.h>, not needed any ↵Kostya Serebryany2017-07-121-3/+0
| | | | | | more llvm-svn: 307858
* [libFuzzer] refactoring in preparation for -reduce_inputs; NFC intendedKostya Serebryany2017-07-125-32/+40
| | | | llvm-svn: 307857
* Add element atomic memset intrinsicDaniel Neilson2017-07-124-1/+109
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
* [AArch64] Only run macro fusion for CPUs with any fusion support.Florian Hahn2017-07-121-1/+3
| | | | | | | | | | | | Reviewers: evandro, t.p.northover, javed.absar Reviewed By: evandro Subscribers: aemerson, rengolin, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34959 llvm-svn: 307851
* Allow clients to specify search order of DynamicLibraries.Frederich Munch2017-07-123-11/+37
| | | | | | | | | | | | | | Summary: Different JITs and other clients of LLVM may have different needs in how symbol resolution should occur. Reviewers: v.g.vassilev, lhames, karies Reviewed By: v.g.vassilev Subscribers: pcanal, llvm-commits Differential Revision: https://reviews.llvm.org/D33529 llvm-svn: 307849
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