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* Enhance integer division emulation support to handle types smaller than 32 bits,Pedro Artigas2013-02-261-0/+104
| | | | | | | | enhancement done the trivial way; by extending inputs and truncating outputs which is addequate for targets with little or no support for integer arithmetic on integer types less than 32 bits. llvm-svn: 176139
* Have a way for a target to opt-out of target-independent fast iselMichael Ilseman2013-02-261-1/+1
| | | | llvm-svn: 176136
* Constant fold vector bitcasts of halves similarly to how floats and doubles ↵Michael Ilseman2013-02-261-6/+8
| | | | | | are folded. Test case included. llvm-svn: 176131
* Add support for autodetection of ADM bdver2.Roman Divacky2013-02-261-1/+4
| | | | llvm-svn: 176130
* Revert r176120 as it caused a failure at static-member.cppManman Ren2013-02-261-4/+1
| | | | llvm-svn: 176129
* [TableGen] Fix ICE on MSVC 2012 Release builds.Michael J. Spencer2013-02-261-1/+2
| | | | llvm-svn: 176125
* Fix PR15332 (patch by Florian Zeitz).Bill Schmidt2013-02-261-4/+5
| | | | | | | | There's no need to generate a stack frame for PPC32 SVR4 when there are no local variables assigned to the stack, i.e., when no red zone is needed. (PPC64 supports a red zone, but PPC32 does not.) llvm-svn: 176124
* Fix auto_ptr is deprecated warningsMatt Arsenault2013-02-261-11/+11
| | | | llvm-svn: 176123
* Debug Info: for static member variables, move AT_MIPS_linkage_name fromManman Ren2013-02-261-1/+4
| | | | | | | | | | | TAG_member inside a class to the specification DIE. Having AT_MIPS_linkage_name on TAG_member caused old gdb (GNU 6.3.50) to error out. Also gcc 4.7 has AT_MIPS_linkage_name on the specification DIE. rdar://problem/13291234 llvm-svn: 176120
* AsmParser: More generic support for integer type suffices.Jim Grosbach2013-02-261-6/+9
| | | | | | | | | | For integer constants, allow 'L', 'UL' as well as 'ULL' and 'LL'. This provides better support for shared headers between .s and .c files that define bunches of constant values. rdar://9321056 llvm-svn: 176118
* Fix typoMatt Arsenault2013-02-261-1/+1
| | | | llvm-svn: 176117
* R600/SI: Add promotion of e32 to e64 in operand foldingChristian Konig2013-02-261-2/+34
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176105
* R600/SI: add VOP mapping functionsChristian Konig2013-02-263-11/+35
| | | | | | | | Make it possible to map between e32 and e64 encoding opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176104
* R600/SI: swap operands if it helps foldingChristian Konig2013-02-261-1/+15
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176103
* R600/SI: add some more instruction flagsChristian Konig2013-02-263-14/+92
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176102
* R600/SI: add post ISel folding for SI v2Christian Konig2013-02-265-23/+231
| | | | | | | | | | Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176101
* R600/SI: add folding helperChristian Konig2013-02-264-0/+30
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176100
* R600/SI: fix VOP3b encoding v2Christian Konig2013-02-262-6/+32
| | | | | | | | | | v2: document why we hardcode VCC for now. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176099
* R600/SI: fix and cleanup SI register definition v2Christian Konig2013-02-262-97/+135
| | | | | | | | | | | | | | | | Prevent producing real strange tablegen code by using proper register sizes, alignments and hierarchy. Also cleanup the unused definitions and add some comments. v2: add SGPR 512 bit registers, stop registers from wrapping around, fix SGPR alignment This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176098
* R600/SI: fix stupid typoChristian Konig2013-02-261-1/+1
| | | | | | | | This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176097
* Fix PR15359.Bill Schmidt2013-02-261-0/+13
| | | | | | | The PowerPC TLS relocation types were not previously added to the necessary list in MCELFStreamer::fixSymbolsInTLSFixups(). Now they are! llvm-svn: 176094
* Unify clang/llvm attributes for asan/tsan/msan (LLVM part)Kostya Serebryany2013-02-267-72/+72
| | | | | | | | | | | | | | | | | | | These are two related changes (one in llvm, one in clang). LLVM: - rename address_safety => sanitize_address (the enum value is the same, so we preserve binary compatibility with old bitcode) - rename thread_safety => sanitize_thread - rename no_uninitialized_checks -> sanitize_memory CLANG: - add __attribute__((no_sanitize_address)) as a synonym for __attribute__((no_address_safety_analysis)) - add __attribute__((no_sanitize_thread)) - add __attribute__((no_sanitize_memory)) for S in address thread memory If -fsanitize=S is present and __attribute__((no_sanitize_S)) is not set llvm attribute sanitize_S llvm-svn: 176075
* Use a DenseMap instead of a std::map for AnalysisID -> Pass* maps. This ↵Michael Ilseman2013-02-261-6/+6
| | | | | | reduces the pass-manager overhead from FPPassManager::runOnFunction() by about 10%. llvm-svn: 176072
* [mips] Use class RegDefsUses to track register defs and uses.Akira Hatanaka2013-02-261-89/+82
| | | | | | No functionality change. llvm-svn: 176070
* [fast-isel] Make sure the FastLowerArguments function checks to make sure theChad Rosier2013-02-262-0/+2
| | | | | | | arguments type is a simple type. rdar://13290455 llvm-svn: 176066
* Refine fix to PR10499, no functionality changeMichael Liao2013-02-251-1/+1
| | | | | | - Put expensive checking after simple one llvm-svn: 176060
* Fix PR10499Michael Liao2013-02-251-1/+1
| | | | | | | - Check whether SSE is available before lowering all 1s vector building with PCMPEQD, which is only available from SSE2 llvm-svn: 176058
* Fix wording.Chad Rosier2013-02-251-3/+4
| | | | llvm-svn: 176055
* [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 orChad Rosier2013-02-252-0/+83
| | | | | | | | | | fewer scalar integer (i32 or i64) arguments. It completely eliminates the need for SDISel for trivial functions. Also, add the new llc -fast-isel-abort-args option, which is similar to -fast-isel-abort option, but for formal argument lowering. llvm-svn: 176052
* pre-RA-sched fix: only reevaluate physreg interferences when necessary.Andrew Trick2013-02-251-33/+61
| | | | | | Fixes rdar:13279013: scheduler was blowing up on select instructions. llvm-svn: 176037
* [ms-inline asm] Add support for the pushad/popad mnemonics.Chad Rosier2013-02-251-4/+2
| | | | | | rdar://13254235 llvm-svn: 176036
* 'Hexadecimal' has two 'a's and only one 'i'.Matt Beaumont-Gay2013-02-252-3/+3
| | | | llvm-svn: 176031
* Fix missing relocation for TLS addressing peephole optimization.Bill Schmidt2013-02-251-0/+3
| | | | | | Report and fix due to Kai Nacke. Testcase update by me. llvm-svn: 176029
* Fix spelling noticed by Duncan.Chandler Carruth2013-02-251-3/+3
| | | | llvm-svn: 176023
* Fix the root cause of PR15348 by correctly handling alignment 0 onChandler Carruth2013-02-252-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | memory intrinsics in the SDAG builder. When alignment is zero, the lang ref says that *no* alignment assumptions can be made. This is the exact opposite of the internal API contracts of the DAG where alignment 0 indicates that the alignment can be made to be anything desired. There is another, more explicit alignment that is better suited for the role of "no alignment at all": an alignment of 1. Map the intrinsic alignment to this early so that we don't end up generating aligned DAGs. It is really terrifying that we've never seen this before, but we suddenly started generating a large number of alignment 0 memcpys due to the new code to do memcpy-based copying of POD class members. That patch contains a bug that rounds bitfield alignments down when they are the first field. This can in turn produce zero alignments. This fixes weird crashes I've seen in library users of LLVM on 32-bit hosts, etc. llvm-svn: 176022
* Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-255-69/+70
| | | | llvm-svn: 176007
* DIBuilder: support structs with vtable pointers in the same way as classesDavid Blaikie2013-02-251-8/+12
| | | | llvm-svn: 176004
* Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-245-61/+39
| | | | llvm-svn: 176002
* Fix PR14364.Bill Schmidt2013-02-244-20/+27
| | | | | | | | | | | This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot(). The proper place to save the frame index for the CR spill slot is in the PPCFunctionInfo object, not the PPCRegisterInfo object. No new test cases, as this just reimplements existing function. Existing tests such as test/CodeGen/PowerPC/crsave.ll are sufficient. llvm-svn: 175998
* CVP: If we have a PHI with an incoming select, try to skip the select.Benjamin Kramer2013-02-241-5/+24
| | | | | | | | | | This is a common pattern with dyn_cast and similar constructs, when the PHI no longer depends on the select it can often be turned into a simpler construct or even get hoisted out of the loop. PR15340. llvm-svn: 175995
* TypoFrancois Pichet2013-02-241-1/+1
| | | | llvm-svn: 175991
* Revert r169638 because it broke Mesa llvmpipe tests.Nadav Rotem2013-02-241-6/+1
| | | | | | Fix PR15239. llvm-svn: 175985
* Make psuedo FEXT_T8I816_ins a custom inserter. It should be expandedReed Kotler2013-02-244-22/+34
| | | | | | as early as possible; which means during instruction selection. llvm-svn: 175984
* Add a use of an otherwise unused variable to remove a warning in non-AssertsCameron Zwarich2013-02-241-0/+1
| | | | | | builds. llvm-svn: 175981
* TwoAddressInstructionPass::tryInstructionTransform() only potentially returnsCameron Zwarich2013-02-241-5/+4
| | | | | | | true when shouldOnlyCommute is false, so we can remove code that checks otherwise. llvm-svn: 175980
* TwoAddrInstructionPass::tryInstructionTransform() has a case where it callsCameron Zwarich2013-02-241-5/+10
| | | | | | | | | | | | | | | | itself recursively with a new instruction that has not been finalized, in order to determine whether to keep the instruction. On 'make check' and test-suite the only cases where the recursive invocation made any transformations were simple instruction commutations, so I am restricting the recursive invocation to do only this. The other cases wouldn't work correctly when updating LiveIntervals, since the new instructions don't have slot indices and LiveIntervals hasn't yet been updated. If the other transformations were actually triggering in any test case it would be possible to support it with a lot of effort, but since they don't it's not worth it. llvm-svn: 175979
* Add new base instruction def for cmpi, cmp, slt and sltu so that def/usesReed Kotler2013-02-231-5/+10
| | | | | | proper. Fixed this already a few days ago for slti. llvm-svn: 175975
* TargetInstrInfo::commuteInstruction() doesn't actually return a new instructionCameron Zwarich2013-02-231-13/+3
| | | | | | | unless it was requested to with an optional parameter that defaults to false, so we don't need to handle that case in TwoAddressInstructionPass. llvm-svn: 175974
* X86: Disable cmov-memory patterns on subtargets without cmov.Benjamin Kramer2013-02-231-6/+8
| | | | | | Fixes PR15115. llvm-svn: 175962
* Make some fixes for LiveInterval repair with debug info. Debug valueCameron Zwarich2013-02-232-2/+6
| | | | | | MachineInstrs don't have a slot index. llvm-svn: 175961
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