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* divide by the result of the gcdSebastian Pop2014-04-081-1/+1
| | | | | | used to fail with 'Step should divide Start with no remainder.' llvm-svn: 205802
* handle special cases when findGCD returns 1Sebastian Pop2014-04-081-1/+6
| | | | | | used to fail with 'Step should divide Start with no remainder.' llvm-svn: 205801
* in findGCD of multiply expr return the gcdSebastian Pop2014-04-081-2/+4
| | | | | | we used to return 1 instead of the gcd llvm-svn: 205800
* [Constant Hoisting][ARM64] Enable constant hoisting for ARM64.Juergen Ributzka2014-04-081-13/+131
| | | | | | | | This implements the target-hooks for ARM64 to enable constant hoisting. This fixes <rdar://problem/14774662> and <rdar://problem/16381500>. llvm-svn: 205791
* RegAlloc: Account for a variable entry block frequencyDuncan P. N. Exon Smith2014-04-082-13/+58
| | | | | | | | | | | | | | | | | | | | Until r197284, the entry frequency was constant -- i.e., set to 2^14. Although current ToT still has a constant entry frequency, since r197284 that has been an implementation detail (which is soon going to change). - r204690 made the wrong assumption for the CSRCost metric. Adjust callee-saved register cost based on entry frequency. - r185393 made the wrong assumption (although it was valid at the time). Update SpillPlacement.cpp::Threshold to be relative to the entry frequency. Since ToT still has 2^14 entry frequency, this should have no observable functionality change. <rdar://problem/14292693> llvm-svn: 205789
* [PowerPC] Don't return false from PPC::isVSLDOIShuffleMaskHal Finkel2014-04-081-1/+1
| | | | | | | | | PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle predicate should be false. Noticed by inspection; no test case (yet). llvm-svn: 205787
* Fix the ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2014-04-081-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 llvm-svn: 205779
* Verifier: Give the right message for bad atomic loadsDuncan P. N. Exon Smith2014-04-081-2/+2
| | | | | | | | Talk about load (not store) on an invalid atomic load. <rdar://problem/16287567> llvm-svn: 205777
* Add -pass-remarks flag to 'opt'.Diego Novillo2014-04-083-1/+61
| | | | | | | | | | | | | | | | | | | | | Summary: This adds support in 'opt' to filter pass remarks emitted by optimization passes. A new flag -pass-remarks specifies which passes should emit a diagnostic when LLVMContext::emitOptimizationRemark is invoked. This will allow the front end to simply pass along the regular expression from its own -Rpass flag when launching the backend. Depends on D3227. Reviewers: qcolombet CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3291 llvm-svn: 205775
* Add support for optimization reports.Diego Novillo2014-04-083-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds backend support for -Rpass=, which indicates the name of the optimization pass that should emit remarks stating when it made a transformation to the code. Pass names are taken from their DEBUG_NAME definitions. When emitting an optimization report diagnostic, the lack of debug information causes the diagnostic to use "<unknown>:0:0" as the location string. This is the back end counterpart for http://llvm-reviews.chandlerc.com/D3226 Reviewers: qcolombet CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3227 llvm-svn: 205774
* X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused ↵NAKAMURA Takumi2014-04-081-1/+3
| | | | | | | DW_LNE_set_address was misemitted on x64. FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8. llvm-svn: 205772
* ARM64: fix fmsub patterns which assumed accum operand was firstTim Northover2014-04-081-4/+7
| | | | | | | | | | Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
* AVX-512: Added fp_to_uint and uint_to_fp patterns.Elena Demikhovsky2014-04-082-0/+13
| | | | llvm-svn: 205754
* Fix a (legacy) PassManager crash that occurs when a ModulePassAndrew Trick2014-04-081-6/+18
| | | | | | | | | indirectly requires a function analysis. This bug was reported by Jason Kim. He included a test case here: http://reviews.llvm.org/D3312 llvm-svn: 205753
* X86: Split the relocation selection upDavid Majnemer2014-04-081-29/+43
| | | | | | | | | | | Before, we would have conditional operators where one side of the operator would be of type RelocationTypeAMD64 and the other is of type RelocationTypeI386. GCC would noisly warn with -Wenum-compare diagnostic. Instead, refactor the code so it is more like the X86 ELF object writer. llvm-svn: 205752
* Tidy up comments a bit.Jim Grosbach2014-04-071-41/+41
| | | | | | Punctuation, grammar, formatting, etc.. llvm-svn: 205749
* ARM64: Range based for loop in ARM64PromoteConstant passJim Grosbach2014-04-071-9/+7
| | | | llvm-svn: 205748
* ARM64: Clean up file header comment a bit.Jim Grosbach2014-04-071-11/+9
| | | | llvm-svn: 205747
* obj2yaml: Use the correct relocation type for different machine typesDavid Majnemer2014-04-071-8/+24
| | | | | | | | | | | | | The IO normalizer would essentially lump I386 and AMD64 relocations together. Relocation types with the same numeric value would then get mapped in appropriately. For example: IMAGE_REL_AMD64_ADDR64 and IMAGE_REL_I386_DIR16 both have a numeric value of one. We would see IMAGE_REL_I386_DIR16 in obj2yaml conversions of object files with a machine type of IMAGE_FILE_MACHINE_AMD64. llvm-svn: 205746
* Reverting commit r205628 due to mips64 issues.Reed Kotler2014-04-073-2/+73
| | | | llvm-svn: 205741
* Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing ↵Andrew Trick2014-04-071-1/+6
| | | | | | | | | | | | | | | | | | | | up compile time. Fixes PR16365 - Extremely slow compilation in -O1 and -O2. The SD scheduler has a quadratic implementation of load clustering which absolutely blows up compile time for large blocks with constant pool loads. The MI scheduler has a better implementation of load clustering. However, we have not done the work yet to completely eliminate the SD scheduler. Some benchmarks still seem to benefit from early load clustering, although maybe by chance. As an intermediate term fix, I just put a nice limit on the number of DAG users to search before finding a match. With this limit there are no binary differences in the LLVM test suite, and the PR16365 test case does not suffer any compile time impact from this routine. llvm-svn: 205738
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-072-0/+12
| | | | llvm-svn: 205732
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-0711-58/+115
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* R600: Replace dyn_cast + assert with castTom Stellard2014-04-071-2/+1
| | | | llvm-svn: 205730
* Use std::swapMatt Arsenault2014-04-071-3/+1
| | | | llvm-svn: 205723
* Use .data() instead of &x[0]Matt Arsenault2014-04-072-18/+21
| | | | llvm-svn: 205722
* Invert the option to enable debug info verification. No functionalEric Christopher2014-04-071-8/+7
| | | | | | change outside of the command line to enable it. llvm-svn: 205713
* Handle vlas during inline cost computation if they'll be turnedEric Christopher2014-04-071-1/+10
| | | | | | | | | | | into a constant size alloca by inlining. Ran a run over the testsuite, no results out of the noise, fixes the testcase in the PR. PR19115. llvm-svn: 205710
* Add NDEBUG markers around debug only function.Eric Christopher2014-04-071-0/+4
| | | | llvm-svn: 205706
* Add debug location information to the vectorizer debug statements.Eric Christopher2014-04-071-5/+29
| | | | | | Patch by Zinovy Nis. llvm-svn: 205705
* [C++11] Make use of 'nullptr' in the Support library.Craig Topper2014-04-0736-182/+184
| | | | llvm-svn: 205697
* Changes in IntelJITEventListener - By Arch RobinsonElena Demikhovsky2014-04-061-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - take->release: LLVM has moved to C++11. MockWrapper became an instance of unique_ptr. - method symbol_iterator::increment disappeared recently, in this revision: r200442 | rafael | 2014-01-29 20:49:50 -0600 (Wed, 29 Jan 2014) | 9 lines Simplify the handling of iterators in ObjectFile. None of the object file formats reported error on iterator increment. In retrospect, that is not too surprising: no object format stores symbols or sections in a linked list or other structure that requires chasing pointers. As a consequence, all error checking can be done on begin() and end(). This reduces the text segment of bin/llvm-readobj in my machine from 521233 to 518526 bytes. My change mimics the change that the revision made to lib/DebugInfo/DWARFContext.cpp . - const_cast: Shut up a warning from gcc. I ran unittests/ExecutionEngine/JIT/Debug+Asserts/JITTests to make sure it worked. - Arch llvm-svn: 205689
* DebugInfo: Support namespace aliases as DW_TAG_imported_declaration instead ↵David Blaikie2014-04-061-24/+23
| | | | | | | | | | | | | | | | of DW_TAG_imported_module I really should read the spec more often (and test GCC more often too). I just assumed that namespace aliases would be the same as using directives, except with a name. But apparently that's not how the DWARF standards suggests they be implemented. DWARF4 provides an example and other non-normative text suggesting that namespace aliases be implemented by named imported declarations intsead of named imported modules. So be it. llvm-svn: 205685
* [Support] Modify LockFileManager::waitForUnlock() to return info about how ↵Argyrios Kyrtzidis2014-04-061-6/+10
| | | | | | the lock was released. llvm-svn: 205683
* Remove unused parameterDavid Blaikie2014-04-051-8/+8
| | | | | | | | | | | Also update a few null pointers in this function to be consistent with new null pointers being added. Patch by Robert Matusewicz! Differential Revision: http://reviews.llvm.org/D3123 llvm-svn: 205682
* AsmParser: add a warning for compatibility parsingSaleem Abdulrasool2014-04-053-0/+10
| | | | | | | | | This adds a warning when linker_private or linker_private_weak is provided and we handle it in a compatible manner. Suggested by Chris Lattner! llvm-svn: 205681
* MachineInstr: introduce explicit_operands and implicit_operands rangesDavid Blaikie2014-04-052-7/+2
| | | | | | | Makes iteration over implicit and explicit machine operands more explicit (har har). Insipired by code review discussion for r205565. llvm-svn: 205680
* ARM: consolidate MachO checks for ARM asm parserSaleem Abdulrasool2014-04-051-84/+28
| | | | | | | | | | | | | | | | | | | This consolidates the duplicated MachO checks in the directive parsing for various directives that are unsupported for Mach-O. The error message change is unimportant as this restores the behaviour to that prior to the addition of the new directive handling. Furthermore, use a more direct check for MachO targeting rather than an indirect feature check of the assembler. Also simplify the test execution command to avoid temporary files. Further more, perform the check in both object and assembly emission. Whether all non-applicable directives are handled is another question. .fnstart is marked as being unsupported, however, the complementary .fnend is not. The additional unwinding directives are also still honoured. This change does not change that, though, it would be good to validate and mark them as being unsupported if they are unsupported for the MachO emission. llvm-svn: 205678
* Simplify compression API by compressing into a SmallVector rather than a ↵David Blaikie2014-04-052-22/+16
| | | | | | | | MemoryBuffer This is the other half of r205676. llvm-svn: 205677
* Simplify compression API by decompressing into a SmallVector rather than a ↵David Blaikie2014-04-053-17/+13
| | | | | | | | | | | | MemoryBuffer This avoids an extra copy during decompression and avoids the use of MemoryBuffer which is a weirdly esoteric device that includes unrelated concepts like "file name" (its rather generic name is a bit misleading). Similar refactoring of zlib::compress coming up. llvm-svn: 205676
* AsmParser: restore LLVM IR compatibility for linker_private{,_weak}Saleem Abdulrasool2014-04-053-0/+17
| | | | | | | | | | | This restores the linker_private and linker_private_weak lexemes to permit translation of the deprecated lexmes. The behaviour is identical to the bitcode handling: linker_private and linker_private_weak are handled as if private had been specified. This enables compatibility with IR generated by LLVM 3.4. Reported on IRC by ki9a! llvm-svn: 205675
* Fixing typo.David Blaikie2014-04-051-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D3154 llvm-svn: 205674
* [PowerPC] Remove unused TM member variable to unbreak buildHal Finkel2014-04-051-3/+2
| | | | | | Fix "error: private field 'TM' is not used [-Werror,-Wunused-private-field]" llvm-svn: 205660
* [PowerPC] Adjust load/store costs in PPCTTIHal Finkel2014-04-041-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | This provides more realistic costs for the insert/extractelement instructions (which are load/store pairs), accounts for the cheap unaligned Altivec load sequence, and for unaligned VSX load/stores. Bad news: MultiSource/Applications/sgefa/sgefa - 35% slowdown (this will require more investigation) SingleSource/Benchmarks/McGill/queens - 20% slowdown (we no longer vectorize this, but it was a constant store that was scalarized) MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2 - 2% slowdown Good news: SingleSource/Benchmarks/Shootout/ary3 - 54% speedup SingleSource/Benchmarks/Shootout-C++/ary - 40% speedup MultiSource/Benchmarks/Ptrdist/ks/ks - 35% speedup MultiSource/Benchmarks/FreeBench/neural/neural - 30% speedup MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt - 20% speedup Unfortunately, estimating the costs of the stack-based scalarization sequences is hard, and adjusting these costs is like a game of whac-a-mole :( I'll revisit this again after we have better codegen for vector extloads and truncstores and unaligned load/stores. llvm-svn: 205658
* [PowerPC] PPCTTI CleanupHal Finkel2014-04-041-4/+0
| | | | | | Remove the declaration of an unimplemented function. llvm-svn: 205657
* Minor change to StackMapLiveness DEBUG output.Andrew Trick2014-04-041-1/+1
| | | | llvm-svn: 205656
* Add DAG parameter to ComputeNumSignBitsForTargetNodeMatt Arsenault2014-04-044-3/+7
| | | | | | | | This way, you can check the number of sign bits in the operands. The depth parameter it already has is pretty useless without this. llvm-svn: 205649
* Fix tabsMatt Arsenault2014-04-041-5/+5
| | | | llvm-svn: 205648
* [mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.Kai Nacke2014-04-042-0/+48
| | | | | | | | | This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
* [PowerPC] Add a full condition code register to make the "cc" clobber workHal Finkel2014-04-041-0/+12
| | | | | | | | gcc inline asm supports specifying "cc" as a clobber of all condition registers. Add just enough modeling of the full register to make this work. Fixed PR19326. llvm-svn: 205630
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