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* Delete getAliasedGlobal.Rafael Espindola2014-05-1615-22/+18
| | | | llvm-svn: 209040
* DebugInfo: Assert rather than conditionalizing when a CU's subprogram list ↵David Blaikie2014-05-161-2/+2
| | | | | | contains declarations. llvm-svn: 209039
* DebugInfo: Handle emitting constants of C++ unicode character type.David Blaikie2014-05-161-2/+3
| | | | | | | | Patch by Stephan Tolksdorf! (with some test case stuff by me) Differential Revision: http://reviews.llvm.org/D3810 llvm-svn: 209037
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-166-34/+112
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600/SI: Add a PredicateControl class for managing TableGen predicatesTom Stellard2014-05-163-28/+22
| | | | | | This was inspired by the PredicateControl class in the MIPS backend. llvm-svn: 209027
* R600/SI: Move tablegen patterns away from instruction defsTom Stellard2014-05-161-30/+31
| | | | llvm-svn: 209026
* R600/SI: Remove unused instructionTom Stellard2014-05-161-7/+0
| | | | llvm-svn: 209025
* R600/SI: Promote f32 SELECT to i32Tom Stellard2014-05-162-6/+2
| | | | llvm-svn: 209024
* R600/SI: Remove duplicate patternTom Stellard2014-05-161-5/+0
| | | | llvm-svn: 209023
* Add comdat key field to llvm.global_ctors and llvm.global_dtorsReid Kleckner2014-05-168-42/+173
| | | | | | | | | | | | | | This allows us to put dynamic initializers for weak data into the same comdat group as the data being initialized. This is necessary for MSVC ABI compatibility. Once we have comdats for guard variables, we can use the combination to help GlobalOpt fire more often for weak data with guarded initialization on other platforms. Reviewers: nlewycky Differential Revision: http://reviews.llvm.org/D3499 llvm-svn: 209015
* Fix a warning in builds without asserts.Rafael Espindola2014-05-161-2/+1
| | | | llvm-svn: 209012
* DebugInfo: Add an assert regarding the subprogram in the subprogram map ↵David Blaikie2014-05-161-0/+1
| | | | | | | | | | matching the abstract subprogram. I'm not sure this is how it'll be going forward (I'd rather prefer the definition to be in the main SP mapping, for various reasons) but this helps me understand how it is today. llvm-svn: 209009
* Fix most of PR10367.Rafael Espindola2014-05-1611-87/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the design of GlobalAlias so that it doesn't take a ConstantExpr anymore. It now points directly to a GlobalObject, but its type is independent of the aliasee type. To avoid changing all alias related tests in this patches, I kept the common syntax @foo = alias i32* @bar to mean the same as now. The cases that used to use cast now use the more general syntax @foo = alias i16, i32* @bar. Note that GlobalAlias now behaves a bit more like GlobalVariable. We know that its type is always a pointer, so we omit the '*'. For the bitcode, a nice surprise is that we were writing both identical types already, so the format change is minimal. Auto upgrade is handled by looking through the casts and no new fields are needed for now. New bitcode will simply have different types for Alias and Aliasee. One last interesting point in the patch is that replaceAllUsesWith becomes smart enough to avoid putting a ConstantExpr in the aliasee. This seems better than checking and updating every caller. A followup patch will delete getAliasedGlobal now that it is redundant. Another patch will add support for an explicit offset. llvm-svn: 209007
* DebugInfo: Assume the CU's Subprogram list only contains definitions.David Blaikie2014-05-161-4/+1
| | | | | | | | | | | DIBuilder maintains this invariant and the current DwarfDebug code could end up doing weird things if it contained declarations (such as putting the definition DIE inside a CU that contained the declaration - this doesn't seem like a good idea, so rather than adding logic to handle this case we'll just ban in for now & cross that bridge if we come to it later). llvm-svn: 209004
* [ARM64] Increases the Sched Model accuracy for Cortex-A53.Chad Rosier2014-05-166-51/+228
| | | | | | | Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D3769 llvm-svn: 209001
* InstSimplify: Improve handling of ashr/lshrDavid Majnemer2014-05-161-1/+21
| | | | | | | | | | | | | | Summary: Analyze the range of values produced by ashr/lshr cst, %V when it is being used in an icmp. Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3774 llvm-svn: 209000
* InstSimplify: Optimize using dividend in sdivDavid Majnemer2014-05-161-0/+4
| | | | | | | | | | | | | | | Summary: The dividend in an sdiv tells us the largest and smallest possible results. Use this fact to optimize comparisons against an sdiv with a constant dividend. Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3795 llvm-svn: 208999
* [ARM64] Fix wrong comment in load/store optimization pass.Tilmann Scheller2014-05-161-1/+1
| | | | | | | | | | | | | | | | ldr x1, [x0, #64] add x0, x0, #64 -> ldr x1, [x0], #64 is not a valid transformation, the correct transformation (and what the code actually does) is: ldr x1, [x0, #64] add x0, x0, #64 -> ldr x1, [x0, #64]! llvm-svn: 208998
* DwarfDebug: Refactor AT_ranges/AT_high_pc+AT_low_pc emission into helper ↵David Blaikie2014-05-162-39/+19
| | | | | | function. llvm-svn: 208997
* [yaml2obj][ELF] Add an optional `Size` field to the YAML section declaration.Simon Atanasyan2014-05-161-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the only method to configure ELF section's content and size is to assign a hexadecimal string to the `Content` field. Unfortunately this way is completely useless when you need to declare a really large section. To solve this problem this patch adds one more optional field `Size` to the `RawContentSection` structure. When yaml2obj generates an ELF file it uses the following algorithm: 1. If both `Content` and `Size` fields are missed create an empty section. 2. If only `Content` field is missed take section length from the `Size` field and fill the section by zero. 3. If only `Size` field is missed create a section using data from the `Content` field. 4. If both `Content` and `Size` fields are provided validate that the `Size` value is not less than size of `Content` data. Than take section length from the `Size`, fill beginning of the section by `Content` and the rest by zero. Examples -------- * Create a section 0x10000 bytes long filled by zero Name: .data Type: SHT_PROGBITS Flags: [ SHF_ALLOC ] Size: 0x10000 * Create a section 0x10000 bytes long starting from 'CA' 'FE' 'BA' 'BE' Name: .data Type: SHT_PROGBITS Flags: [ SHF_ALLOC ] Content: CAFEBABE Size: 0x10000 The patch reviewed by Michael Spencer. llvm-svn: 208995
* Re-enable inline memcpy expansion for Thumb1.James Molloy2014-05-162-6/+5
| | | | | | Patch by Moritz Roth! llvm-svn: 208994
* Small dyn_cast and auto cleanup.Rafael Espindola2014-05-161-3/+3
| | | | llvm-svn: 208993
* Fix the Load/Store optimization pass to work with Thumb1.James Molloy2014-05-162-38/+238
| | | | | | Patch by Moritz Roth! llvm-svn: 208992
* Enable the Load/Store optimization pass for Thumb1 but make it return ↵James Molloy2014-05-162-8/+14
| | | | | | | | immediately for now. Patch by Moritz Roth! llvm-svn: 208991
* Fix a few comment typos and style issues.James Molloy2014-05-161-16/+17
| | | | | | Patch by Moritz Roth! llvm-svn: 208990
* [mips][mips64r6] Add SELEQZ and SELNEZ instructionsZoran Jovanovic2014-05-161-2/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D3743 llvm-svn: 208987
* Change the GlobalAlias constructor to look a bit more like GlobalVariable.Rafael Espindola2014-05-167-20/+33
| | | | | | | This is part of the fix for pr10367. A GlobalAlias always has a pointer type, so just have the constructor build the type. llvm-svn: 208983
* [mips][mips64r6] Add Compact indexed jumps.Zoran Jovanovic2014-05-165-2/+81
| | | | | | Differential Revision: http://reviews.llvm.org/D3707 llvm-svn: 208981
* Fix hardcoded slash to native path seperator which was exposed from ↵Yaron Keren2014-05-163-2/+9
| | | | | | | | llvm::sys::path. http://reviews.llvm.org/D3687 llvm-svn: 208980
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-168-142/+12
| | | | | | | | | | | | This reverts commit r208934. The patch depends on aliases to GEPs with non zero offsets. That is not supported and fairly broken. The good news is that GlobalAlias is being redesigned and will have support for offsets, so this patch should be a nice match for it. llvm-svn: 208978
* [mips][mips64r6] Add Compact zero-compare branch-and-link instructionsZoran Jovanovic2014-05-161-6/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D3718 llvm-svn: 208977
* MergeFunctions Pass, introduced total ordering among GEP operations.Stepan Dyatkovskiy2014-05-161-23/+41
| | | | | | | | | | Patch replaces old isEquivalentGEP implementation, and changes type of comparison result from bool (equal or not) to {-1, 0, 1} (less, equal, greater). This patch belongs to patch series that improves MergeFunctions performance time from O(N*N) to O(N*log(N)). llvm-svn: 208976
* MC: Add DwarfTypesDWOSection also to MCCOFF.NAKAMURA Takumi2014-05-161-0/+4
| | | | llvm-svn: 208975
* [mips][mips64r6] Add compact branch instructionsZoran Jovanovic2014-05-166-10/+236
| | | | | | Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
* MergeFunctions Pass, introduced total ordering among operations.Stepan Dyatkovskiy2014-05-161-50/+135
| | | | | | | | | | Patch replaces old isEquivalentOperation implementation, and changes type of comparison result from bool (equal or not) to {-1, 0, 1} (less, equal, greater). This patch belongs to patch series that improves MergeFunctions performance time from O(N*N) to O(N*log(N)). llvm-svn: 208973
* [mips][mips64r6] Add LWPC and LWUPC instructionsZoran Jovanovic2014-05-162-4/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D3788 llvm-svn: 208971
* [mips][mips64r6] Add Floating Point Compare setting Mask - CMP.condn.fmtZoran Jovanovic2014-05-162-2/+111
| | | | | | Differential Revision: http://reviews.llvm.org/D3750 llvm-svn: 208970
* TableGen: fix operand counting for aliasesTim Northover2014-05-163-70/+6
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* ARM64: disable printing of "fcmXY ..., #0" aliasesTim Northover2014-05-161-2/+2
| | | | | | | | | The canonical syntax is "fcmXY ..., #0.0". This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208968
* AArch64: disable printing of add/sub aliasTim Northover2014-05-161-1/+2
| | | | | | | | | | This alias appears not to have an appropriate PrintMethod. Normally, I'd look into it, but since AArch64 is disappearing soon it's probably not worth it. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208967
* Sparc: disable printing of jmp/call aliases (C++ does it)Tim Northover2014-05-161-4/+4
| | | | | | | | | | These aliases are handled entirely in C++ and only having TableGen InstAliases for some of them was confusing LLVM. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208966
* Sparc: disable printing on longer "brX,pt" aliasesTim Northover2014-05-161-2/+2
| | | | | | | This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208965
* Mips: don't print subu alias for addiuTim Northover2014-05-161-2/+2
| | | | | | | | | | Certainly not without having a custom PrintMethod to invert the immediate beforehand. But probably not at all. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208964
* X86: disable printing of bare "mov" aliasesTim Northover2014-05-161-3/+3
| | | | | | | | | | | In AT&T syntax, we should probably print the full "movl" or "movw". TableGen used to ignore these aliases because it was miscounting the number of operands. This fixes the issue. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208963
* AArch64: disable printing of MOV -> MOVZ aliasesTim Northover2014-05-161-1/+1
| | | | | | | | | | Actually, MOV sometimes is canonical, but for now this is a better approximation than what's there. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208962
* ARM64: disable printing of swapped compare-mask aliasesTim Northover2014-05-161-12/+12
| | | | | | | | | | You can perform (say) an fcmle operation by swapping the operands on an fcmge, but it shouldn't be printed like that. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208961
* ARM64: disable printing of LDUR -> LDR aliasesTim Northover2014-05-161-24/+40
| | | | | | | | | | We accept "ldr w3, [x1, #-1]" as a convenience, but we should still print the canonical "ldur" form. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208960
* ARM64: give TST aliases priority over ANDS.Tim Northover2014-05-161-10/+10
| | | | | | | | | | If an ANDS instruction has Rd == ZR it should be printed as TST since its only effect is on the flags register NZCV. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208959
* ARM64: give MOV priority over shorter ORR when printing aliases.Tim Northover2014-05-161-11/+17
| | | | | | | | | MOV is almost always the right thing to print if possile. People understand it. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208958
* ARM64: give NEG priority over SUB when printing aliases.Tim Northover2014-05-162-23/+21
| | | | | | | | | | For example, the full instruction "sub w0, wzr, w1, uxtw" could print as either "neg w0, w1" or "sub w0, wzr, w1". The former is better. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208957
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