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* Add support for files with more than 65280 sections. No testcase sinceRafael Espindola2010-10-311-42/+109
| | | | | | it would be a bit too big :-) llvm-svn: 117849
* Make sure we have a legal type (and simple) before continuing.Eric Christopher2010-10-301-1/+4
| | | | llvm-svn: 117848
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-2/+2
| | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. llvm-svn: 117831
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-302-14/+20
| | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
* really zap alias.Chris Lattner2010-10-301-1/+0
| | | | llvm-svn: 117824
* move fcompi alias to .td file and zap some useless code.Chris Lattner2010-10-302-11/+1
| | | | llvm-svn: 117823
* move rep aliases to td fileChris Lattner2010-10-302-5/+7
| | | | llvm-svn: 117822
* move sal aliases to .td file.Chris Lattner2010-10-302-5/+5
| | | | llvm-svn: 117821
* fix an encoding mismatch where "sal %eax, 1" was not using the short encodingChris Lattner2010-10-301-1/+1
| | | | | | for shl. Caught by inspection. llvm-svn: 117820
* move a bunch more aliases from .cpp -> .td file.Chris Lattner2010-10-302-22/+27
| | | | llvm-svn: 117819
* move cmov aliases to .td file.Chris Lattner2010-10-302-49/+25
| | | | llvm-svn: 117818
* move setcc and jcc aliases from .cpp to .tdChris Lattner2010-10-302-14/+28
| | | | llvm-svn: 117817
* move some code.Chris Lattner2010-10-301-33/+35
| | | | llvm-svn: 117816
* implement (and document!) the first kind of MC assembler alias, which Chris Lattner2010-10-302-15/+23
| | | | | | | just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
* Now that the MallocInst no longer exists, this workaround forDuncan Sands2010-10-301-5/+0
| | | | | | it claiming not to have side-effects is no longer needed. llvm-svn: 117789
* Add FIXME.Jim Grosbach2010-10-301-0/+2
| | | | llvm-svn: 117787
* Clean up comments.Jim Grosbach2010-10-301-1/+5
| | | | llvm-svn: 117785
* If a function does a volatile load from a global constant, do notDuncan Sands2010-10-301-4/+4
| | | | | | | | | consider it to be readonly. In fact, don't even consider it to be readonly if it does a volatile load from an AllocaInst either (it is debatable as to whether readonly would be correct or not in this case; play safe for the moment). This fixes PR8279. llvm-svn: 117783
* Tidy up.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117782
* stay out of the reserved namespaceChris Lattner2010-10-301-6/+6
| | | | llvm-svn: 117773
* simplify this code.Chris Lattner2010-10-301-8/+4
| | | | llvm-svn: 117771
* split MaybeParseRegister into its two logical uses, eliminating malloc+free ↵Chris Lattner2010-10-301-35/+38
| | | | | | traffic. llvm-svn: 117769
* Avoid re-evaluating MI.getNumOperands() every iteration of the loop.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117766
* Include MachineBasicBlock numbers in viewCFG() output.Jakob Stoklund Olesen2010-10-301-8/+6
| | | | llvm-svn: 117765
* Make sure copies are inserted after any exception handling labels at the top ofJakob Stoklund Olesen2010-10-301-1/+1
| | | | | | a basic block. llvm-svn: 117764
* Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is neededJakob Stoklund Olesen2010-10-301-0/+7
| | | | | | elsewhere. llvm-svn: 117763
* Disable more of physical register live intervals verification.Jakob Stoklund Olesen2010-10-301-2/+3
| | | | llvm-svn: 117762
* Print out register class of spilled register.Jakob Stoklund Olesen2010-10-301-2/+4
| | | | llvm-svn: 117761
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-305-131/+61
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-304-0/+23
| | | | llvm-svn: 117753
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-3/+9
| | | | | | conditional. Check for those instructions explicitly. llvm-svn: 117747
* Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng2010-10-291-50/+45
| | | | | | defs. rdar://8610857. llvm-svn: 117745
* Remove hard tab characters.Jim Grosbach2010-10-291-3/+3
| | | | llvm-svn: 117742
* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117741
* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117740
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-293-3/+3
| | | | | | encoder functions. llvm-svn: 117738
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-293-4/+12
| | | | llvm-svn: 117737
* Be more strict on when we produce an undefined reference. In gas a file withRafael Espindola2010-10-291-1/+4
| | | | | | | | | | | | | | | | | | | | | | | just .type foo,@object will produce an undefined reference to foo. On the other hand, a file with just .weakref bar, foo will not. It is somewhat hard to support both in MC since both statements should create the symbols. It should be possible if we really need to by adding to the flags, but hopefully that is not necessary. With this patch we do not produce a undefined reference in any of those cases. The assembly file needs an actual use for the undefined reference to be present. This is in preparation for a patch implementing .weakref. llvm-svn: 117735
* Clean up indentation and other whitespace.Bob Wilson2010-10-291-11/+9
| | | | llvm-svn: 117728
* Remove trailing whitespace.Bob Wilson2010-10-291-70/+69
| | | | llvm-svn: 117727
* Fix 80-column violation.Bob Wilson2010-10-291-1/+2
| | | | llvm-svn: 117722
* Change instcombine's getShuffleMask to represent undef with negative values.Bob Wilson2010-10-291-40/+36
| | | | | | | | This code had previously used 2*N, where N is the mask length, to represent undef. That is not safe because the shufflevector operands may have more than N elements -- they don't have to match the result type. llvm-svn: 117721
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-5/+0
| | | | llvm-svn: 117720
* Make instcombine a little more aggressive in combining vector shuffles.Bob Wilson2010-10-291-15/+22
| | | | | | | | Allow splats even if they don't match either of the original shuffles, possibly due to undef entries in the shuffles masks. Radar 8597790. Also fix some 80-column violations. llvm-svn: 117719
* add FIXMEJim Grosbach2010-10-291-0/+5
| | | | llvm-svn: 117718
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-294-45/+32
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* Handle comparison values we already have - this fixes the consumer-typesetEric Christopher2010-10-291-4/+65
| | | | | | failure for llvm-gcc on arm fast isel. llvm-svn: 117710
* Give up on doing in-line instruction simplification during correlated value ↵Owen Anderson2010-10-291-10/+1
| | | | | | | | | | | | | propagation. Instruction simplification needs to be guaranteed never to be run on an unreachable block. However, earlier block simplifications may have changed the CFG to make block that were reachable when we began our iteration unreachable by the time we try to simplify them. (Note that this also means that our depth-first iterators were potentially being invalidated). This should not have a large impact on code quality, since later runs of instcombine should pick up these simplifications. Fixes PR8506. llvm-svn: 117709
* ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need toJim Grosbach2010-10-291-55/+0
| | | | | | handle it in the asm lowering. llvm-svn: 117707
* Fix typo.Jim Grosbach2010-10-291-1/+1
| | | | llvm-svn: 117703
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