| Commit message (Collapse) | Author | Age | Files | Lines |
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if we are given a Layout object, even in cases when the value is not fixed.
This will be needed by the final patch for the dwarf .loc support to size a
new MCDwarf fragment needed to build and emit dwarf line number tables.
llvm-svn: 115155
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llvm-svn: 115154
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for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
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reduces the amount of malloc calls and may reduce memory overhead.
Some numbers:
ASTContext stats, clang -cc1 -disable-free -fsyntax-only Cocoa_h.m
without dynamic growth | with dynamic growth
Number of memory regions: 3158 | Number of memory regions: 432
Bytes used: 12333185 | Bytes used: 12333185
Bytes allocated: 12935168 | Bytes allocated: 12800000
Bytes wasted: 601983 (includes alignment, etc) | Bytes wasted: 466815 (includes alignment, etc)
ASTContext stats, clang -cc1 -disable-free -fsyntax-only on clang's ASTReader.cpp
without dynamic growth | with dynamic growth
Number of memory regions: 10987 | Number of memory regions: 551
Bytes used: 42910356 | Bytes used: 42910356
Bytes allocated: 45002752 | Bytes allocated: 44711936
Bytes wasted: 2092396 (includes alignment, etc) | Bytes wasted: 1801580 (includes alignment, etc)
llvm-svn: 115151
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llvm-svn: 115149
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llvm-svn: 115147
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the very unlikely case that someone passes an integer > i64 to strchr.
llvm-svn: 115144
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specifically assert on unexpected flags.
llvm-svn: 115143
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time. That way, the EntrySize field is initialized for other code paths,
namely, the .ll -> .o code path.
llvm-svn: 115141
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llvm-svn: 115136
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llvm-svn: 115135
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With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
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Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
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constructing a section. Test for a few cases also included.
llvm-svn: 115132
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resolved or not. Different object files have different restrictions and
different native assemblers have different idiosyncrasies we want to emulate
for now.
Move the existing MachO logic to the new place and implement an ELF one that
gets fixups to globals right.
llvm-svn: 115131
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Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
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the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
llvm-svn: 115129
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to an empty PrintSpecial()
llvm-svn: 115128
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(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
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llvm-svn: 115122
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
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llvm-svn: 115116
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solution for the Win32 ACCESS_DENIED lit error.
llvm-svn: 115114
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llvm-svn: 115111
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llvm-svn: 115107
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for generic call handling.
llvm-svn: 115105
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llvm-svn: 115102
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llvm-svn: 115100
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pipeline forwarding path.
llvm-svn: 115098
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llvm-svn: 115097
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llvm-svn: 115095
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a context.
llvm-svn: 115094
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llvm-svn: 115091
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llvm-svn: 115089
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boolean for isArtificial.
This is a backword compatible change.
llvm-svn: 115084
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the CFG, but HAD modified some PHI nodes. Fixes PR8174.
llvm-svn: 115083
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still having predecessor, if it is part of a self-loop.
Because of this, we cannot use the Simplify* APIs, as they can assert-fail on unreachable code. Since it's not easy to determine
if a given threading will cause a block to become unreachable, simply defer simplifying simplification to later InstCombine and/or
DCE passes.
llvm-svn: 115082
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llvm-svn: 115076
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llvm-svn: 115067
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which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
llvm-svn: 115066
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lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'
llvm-svn: 115064
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for LLVM 2.9
llvm-svn: 115062
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instructions.
llvm-svn: 115061
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llvm-svn: 115053
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
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llvm-svn: 115043
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One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
llvm-svn: 115038
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llvm-svn: 115037
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opportunities on thumb2
added some doxygen on the way
llvm-svn: 115033
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llvm-svn: 115029
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