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* Fix indentation alignment of a declaration in MipsMCCodeEmitter.cppMark Seaborn2013-12-291-2/+2
| | | | llvm-svn: 198162
* Store the global variable that's created so that it's reclaimed afterwards.Bill Wendling2013-12-291-1/+3
| | | | | | | | This plugs a memory leak in ARM's FastISel by storing the GV in Module so that it's reclaimed. PR17978 llvm-svn: 198160
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-293-40/+83
| | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
* [SparcV9] For codegen generated library calls that return float, set inreg ↵Venkatraman Govindaraju2013-12-291-0/+6
| | | | | | | | flag manually in LowerCall(). This makes the sparc backend to generate Sparc64 ABI compliant code. llvm-svn: 198149
* Make more of the x86 lowering helper functions static.Craig Topper2013-12-292-12/+11
| | | | llvm-svn: 198146
* [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.Venkatraman Govindaraju2013-12-291-8/+60
| | | | | | Also, pass fp128 arguments to varargs through integer registers if necessary. llvm-svn: 198145
* Switch from EVT to MVT in more of the x86 instruction lowering code.Craig Topper2013-12-291-46/+44
| | | | llvm-svn: 198144
* CodeGen: silence a C++11 feature warningSaleem Abdulrasool2013-12-281-1/+1
| | | | llvm-svn: 198133
* ARM IAS: handle errors more appropriatelySaleem Abdulrasool2013-12-281-98/+176
| | | | | | | | | | | Directive parsers must return false if the target assembler is interested in handling the directive. The Error member function returns true always. Using the 'return Error()' pattern would incorrectly indicate to the general parser that the target was not interested in the directive, when in reality it simply encountered a badly formed directive or some other error. This corrects the behaviour to ensure that the parser behaves appropriately. llvm-svn: 198132
* Uninitialized variable (in never taken path) after factoring.Andrew Trick2013-12-281-1/+1
| | | | llvm-svn: 198131
* New machine model for cortex-a9. Schedule for resources and latency.Andrew Trick2013-12-281-2/+8
| | | | | | | | | Schedule more conservatively to account for stalls on floating point resources and latency. Use the AGU resource to model latency stalls since it's shared between FP and LD/ST instructions. This might not be completely accurate but should work well in practice. llvm-svn: 198125
* Added debugging options: -misched-only-func/blockAndrew Trick2013-12-281-0/+13
| | | | llvm-svn: 198124
* The Cortex-A9 machine model is incomplete. Mark it as such.Andrew Trick2013-12-281-0/+5
| | | | | | | | | | Many vector operations never had itineraries. Since the new machine model was a mapping from existing itinerary classes, we don't have a model for these. We still want to migrate A9 even though no one has invested in a complete model, so mark it incomplete to avoid the scheduler asserting. llvm-svn: 198123
* Add a PostMachineScheduler pass with generic implementation.Andrew Trick2013-12-281-284/+522
| | | | | | | | | | | | | | | | | | | | | | | | | PostGenericScheduler uses either the new machine model or the hazard checker for top-down scheduling. Most of the infrastructure for PreRA machine scheduling is reused. With a some tuning, this should allow MachineScheduler to be default for all ARM targets, including cortex-A9, using the new machine model. Likewise, with additional tuning, it should be able to replace PostRAScheduler for all targets. The PostMachineScheduler pass does not currently run the AntiDepBreaker. There is less need for it on targets that are already running preRA MachineScheduler. I want to prove it's necessary before committing to the maintenance burden. The PostMachineScheduler also currently removes kill flags and adds them all back later. This is a bit ridiculous. I'd prefer passes to directly use a liveness utility than rely on flags. A test case that enables this scheduler will be included in a subsequent checkin that updates the A9 model. llvm-svn: 198122
* Move the PostRA scheduler's fixupKills function for reuse.Andrew Trick2013-12-282-163/+150
| | | | llvm-svn: 198121
* Stub out a PostMachineScheduler pass.Andrew Trick2013-12-283-1/+82
| | | | | | Placeholder and boilerplate for a PostRA MachineScheduler pass. llvm-svn: 198120
* Factor MI-Sched in preparation for post-ra scheduling support.Andrew Trick2013-12-286-212/+336
| | | | | | | | Factor the MachineFunctionPass into MachineSchedulerBase. Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive. llvm-svn: 198119
* Use getSimpleValueType in a few spots where the type should be simple.Craig Topper2013-12-281-4/+4
| | | | llvm-svn: 198117
* Minor indentation fix to match other switch statements. Change ↵Craig Topper2013-12-281-60/+60
| | | | | | llvm_unreachable text to match similar places. llvm-svn: 198116
* Mark some Type and EVT methods as LLVM_READONLY.Craig Topper2013-12-281-1/+1
| | | | llvm-svn: 198115
* [X86] Teach the backend how to fold target specific dag node for packedAndrea Di Biagio2013-12-281-2/+53
| | | | | | | | | | | | | | | | | | | | vector shift by immedate count (VSHLI/VSRLI/VSRAI) into a build_vector when the vector in input to the shift is a build_vector of all constants or UNDEFs. Target specific nodes for packed shifts by immediate count are in general introduced by function 'getTargetVShiftByConstNode' (in X86ISelLowering.cpp) when lowering shift operations, SSE/AVX immediate shift intrinsics and (only in very few cases) SIGN_EXTEND_INREG dag nodes. This patch adds extra rules for simplifying vector shifts inside function 'getTargetVShiftByConstNode'. Added file test/CodeGen/X86/vec_shift5.ll to verify that packed shifts by immediate are correctly folded into a build_vector when the input vector to the shift dag node is a vector of constants or undefs. llvm-svn: 198113
* AsmParser: cleanup diagnostics for .rep/.reptSaleem Abdulrasool2013-12-281-3/+10
| | | | | | | Avoid double diagnostics for invalid expressions for count. Improve caret location for negative count. llvm-svn: 198099
* IAS: support .rep as an alias for .reptSaleem Abdulrasool2013-12-281-5/+8
| | | | | | | The GNU assembler supports .rep as an alias for .rept. This simply creates the alias for it and introduces a test for both .rept and .rep. llvm-svn: 198097
* ARMAsmParser: fix typo in commentSaleem Abdulrasool2013-12-281-1/+1
| | | | llvm-svn: 198095
* Disable transforms that introduce calls to exp10*() on Linux due toChandler Carruth2013-12-281-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | widespread glibc bugs. The glibc implementation of exp10 has a very serious precision bug in version 2.15 (and older versions). This is still very widely used (the current Ubuntu LTS for example uses it) and so it isn't reasonable to make transforms that produce these functions. This fixes many miscompiles introduced when we started transforming pow(10.0, ...) into exp10, and it may have fixed other latent miscompiles where exp10 provided sufficient precision but exp10f did not. This is all really horrible. The primary bug has been fixed for over a year and glibc 2.18 works correctly for the test cases I have, but it will be 2017 before the LTS using 2.15 is no longer supported by Ubuntu (and thus reasonable for folks to be relying on). =[ We're either going to need to live without these optimizations, or find a way to switch behavior more dynamically than using simply the fact that the OS is "Linux". To make matters worse, there appears to be significant testing and fixing of numerous other bugs in the exp10 family of functions right now in glibc. While those haven't been causing problems I've seen in the wild, it gives me concerns that we may need to wait until an even later release of glibc before we can reliably transform code into exp10. llvm-svn: 198093
* Remove AsmPrinter::needsRelocationsForDwarfStringPool() since it'sEric Christopher2013-12-282-6/+3
| | | | | | | just calling into MAI and is only abstracting for a single interface that we actually need to check in multiple places. llvm-svn: 198092
* Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR ofAndrea Di Biagio2013-12-272-0/+39
| | | | | | | | | | | | | | | | | | | | ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C llvm-svn: 198084
* DebugInfo: Remove dead code, DICompositeType::addMember(DIDescriptor D)David Blaikie2013-12-271-13/+0
| | | | | | | | | | | | | | It's no longer necessary to lazily add members to the DICompositeType member list. Instead any lazy members (special member functions and member template instantiations) are added to the parent late based on their context link, the same way that nested types have always been handled (never being in the member list - just added to the parent DIE lazily based on context). Clang's been updated not to use this function anymore as it improves type unit consistency by never emitting lazy members in type units. llvm-svn: 198079
* Use two variables here rather than reusing (and abusing) one. This isChandler Carruth2013-12-271-6/+6
| | | | | | | much more clear to me. I meant to make this change before committing the original patch, but forgot to merge it in. Sorry. llvm-svn: 198069
* Introduce a simple line-by-line iterator type into the Support library.Chandler Carruth2013-12-272-0/+69
| | | | | | | | | | | | | | | | | | | This is an iterator which you can build around a MemoryBuffer. It will iterate through the non-empty, non-comment lines of the buffer as a forward iterator. It should be small and reasonably fast (although it could be made much faster if anyone cares, I don't really...). This will be used to more simply support the text-based sample profile file format, and is largely based on the original patch by Diego. I've re-worked the style of it and separated it from the work of producing a MemoryBuffer from a file which both simplifies the interface and makes it easier to test. The style of the API follows the C++ standard naming conventions to fit in better with iterators in general, much like the Path and FileSystem interfaces follow standard-based naming conventions. llvm-svn: 198068
* TLI: Make exp10* avaiable on Linux/Mac/iOS and unavailable elsewhereReid Kleckner2013-12-261-34/+33
| | | | | | | | This makes it unavailable on NetBSD, Android, etc. Patch by Brad Smith! llvm-svn: 198056
* Recognize armv7a and friends as aliases for armv7-a etc. for the purposeJoerg Sonnenberger2013-12-264-0/+11
| | | | | | of architecture naming. llvm-svn: 198043
* ARM IAS: support .even directiveSaleem Abdulrasool2013-12-261-0/+25
| | | | | | | The .even directive aligns content to an evan-numbered address. This is an ARM specific directive applicable to any section. llvm-svn: 198031
* [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju2013-12-2611-70/+416
| | | | llvm-svn: 198030
* [Sparc] Add target specific MCExpr class to handle sparc specific modifiers ↵Venkatraman Govindaraju2013-12-263-0/+183
| | | | | | like %hi, %lo, etc., llvm-svn: 198029
* [Sparc] Add MCInstPrinter implementation for SPARC.Venkatraman Govindaraju2013-12-258-4/+188
| | | | llvm-svn: 198028
* [Mips] Does not take in account 'use-soft-float' attribute's value whenSimon Atanasyan2013-12-251-2/+1
| | | | | | | | consider to generate stubs for mips16 hard-float mode. The patch reviewed by Reed Kotler. llvm-svn: 198019
* [ASan] Fix the test for __asan_gen_ globals and actually fix ↵Alexander Potapenko2013-12-251-2/+2
| | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=17976 by setting the correct linkage (as stated in the bug). llvm-svn: 198018
* [ASan] Make sure none of the __asan_gen_ global strings end up in the symbol ↵Alexander Potapenko2013-12-251-10/+21
| | | | | | | | | table, add a test. This should fix http://llvm.org/bugs/show_bug.cgi?id=17976 Another test checking for the global variables' locations and prefixes on Darwin will be committed separately. llvm-svn: 198017
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-255-122/+315
| | | | llvm-svn: 198013
* Support for microMIPS load effective address.Zoran Jovanovic2013-12-252-2/+6
| | | | llvm-svn: 198010
* Support for microMIPS FPU instructions 2.Zoran Jovanovic2013-12-255-37/+147
| | | | llvm-svn: 198009
* AVX-512: Result type of scalar SETCC is MVT::i1 for AVX-512.Elena Demikhovsky2013-12-252-8/+10
| | | | llvm-svn: 198008
* [AArch64]Fix a problem that the register order of fmls/fmla by element is ↵Hao Liu2013-12-251-1/+1
| | | | | | | | | | | incorrect. E.g. the codegen result is fmls v1.2s, v0.2s, v2.s[3] which is expected to be fmls v0.2s, v1.2s, v2.s[3] llvm-svn: 198001
* Fix typo.Richard Sandiford2013-12-241-1/+1
| | | | llvm-svn: 197986
* [SystemZ] Use interlocked-access 1 instructions for CodeGenRichard Sandiford2013-12-245-69/+118
| | | | | | | | | ...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. llvm-svn: 197985
* [SystemZ] Add MC support for interlocked-access 1 instructionsRichard Sandiford2013-12-245-3/+41
| | | | llvm-svn: 197984
* AVX-512: fixed some patterns for MVT::i1Elena Demikhovsky2013-12-243-19/+46
| | | | llvm-svn: 197981
* [AArch64]Add patterns to match normal shift nodes: shl, sra and srl.Hao Liu2013-12-241-0/+55
| | | | llvm-svn: 197969
* [AArch64 NEON] Fix a bug when lowering BUILD_VECTOR.Kevin Qin2013-12-241-1/+4
| | | | | | | | | DAG.getVectorShuffle() doesn't always return a vector_shuffle node. If mask is the exact sequence of it's operand(For example, operand_0 is v8i8, and the mask is 0, 1, 2, 3, 4, 5, 6, 7), it will directly return that operand. So a check is added here. llvm-svn: 197967
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