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authorHao Liu <Hao.Liu@arm.com>2013-12-25 07:12:34 +0000
committerHao Liu <Hao.Liu@arm.com>2013-12-25 07:12:34 +0000
commit83799741fb289d523f05c49f4beb562986637c43 (patch)
tree90ca290bc53e9f52c06b173b48cf13c8caf27954 /llvm/lib
parent6322e036aa7ef1bf97b10708765a80d661fff672 (diff)
downloadbcm5719-llvm-83799741fb289d523f05c49f4beb562986637c43.tar.gz
bcm5719-llvm-83799741fb289d523f05c49f4beb562986637c43.zip
[AArch64]Fix a problem that the register order of fmls/fmla by element is incorrect.
E.g. the codegen result is fmls v1.2s, v0.2s, v2.s[3] which is expected to be fmls v0.2s, v1.2s, v2.s[3] llvm-svn: 198001
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrNEON.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrNEON.td b/llvm/lib/Target/AArch64/AArch64InstrNEON.td
index 95e54b8ecf1..b1da41853d5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrNEON.td
@@ -7258,7 +7258,7 @@ class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
ValueType ResTy, ValueType OpTy,
SDPatternOperator coreop>
: Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
- (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
+ (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
(INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
// Pattern for lane 0
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