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* two changes:Chris Lattner2009-03-241-45/+29
| | | | | | | | | | | 1. Make instcombine always canonicalize trunc x to i1 into an icmp(x&1). This exposes the AND to other instcombine xforms and is more of what the code generator expects. 2. Rewrite the remaining trunc pattern match to use 'match', which simplifies it a lot. llvm-svn: 67635
* Change JIT for different layout of fp80.Dale Johannesen2009-03-241-5/+5
| | | | llvm-svn: 67629
* more tidying: name the components of PhysReg in the case whenChris Lattner2009-03-241-8/+9
| | | | | | the target constraint specifies a specific physreg. llvm-svn: 67618
* Tidy a bit more.Chris Lattner2009-03-241-3/+3
| | | | llvm-svn: 67617
* simplify this code a bit now that "allocation to a vreg class" can neverChris Lattner2009-03-241-16/+13
| | | | | | fail. llvm-svn: 67616
* I was convinced that it's ok to allow a second i8 return valueDan Gohman2009-03-241-7/+8
| | | | | | | | | | | to be returned in DL. LLVM's multiple-return-value support is not ABI-conforming; front-ends that wish to have code emitted that conforms to an ABI are currently expected to make arrangements for this on their own rather than assuming that multiple-return-values will automatically do the right thing. This commit doesn't fundamentally change this situation. llvm-svn: 67588
* Minor compile-time optimization; don't bother checkingDan Gohman2009-03-241-1/+1
| | | | | | | canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. llvm-svn: 67587
* Add a pre-pass to the burr-list scheduler which makes adjustments toDan Gohman2009-03-241-0/+120
| | | | | | | | | help out the register pressure reduction heuristics in the case of nodes with multiple uses. Currently this uses very conservative heuristics, so it doesn't have a broad impact, but in cases where it does help it can make a big difference. llvm-svn: 67586
* Do not emit comments unless -asm-verbose.Evan Cheng2009-03-245-126/+221
| | | | llvm-svn: 67580
* Use a SmallPtrSet instead of std::set.Dale Johannesen2009-03-231-2/+2
| | | | llvm-svn: 67578
* Fix a bug in spill weight computation. If the alias is a super-register, and ↵Evan Cheng2009-03-231-7/+34
| | | | | | | | | | | the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. e.g. allocating for GR32, bh is not used, updating bl spill weight. bl should get the same spill weight otherwise it will be choosen as a spill candidate since spilling bh doesn't make ebx available. This fix PR2866. llvm-svn: 67574
* Fix internal representation of fp80 to be theDale Johannesen2009-03-238-27/+83
| | | | | | | | | | same as a normal i80 {low64, high16} rather than its own {high64, low16}. A depressing number of places know about this; I think I got them all. Bitcode readers and writers convert back to the old form to avoid breaking compatibility. llvm-svn: 67562
* When unfolding a load during scheduling, the new operator node hasDan Gohman2009-03-231-3/+6
| | | | | | | | | | a data dependency on the load node, so it really needs a data-dependence edge to the load node, even if the load previously existed. And add a few comments. llvm-svn: 67554
* Fix PR3391 and PR3864. Reg allocator infinite looping.Evan Cheng2009-03-232-6/+14
| | | | llvm-svn: 67544
* Don't set SUnit::hasPhysRegDefs to true unless the defs areDan Gohman2009-03-231-1/+4
| | | | | | actually have uses, which reflects the way it's used. llvm-svn: 67540
* Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman2009-03-231-14/+19
| | | | | | | in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. llvm-svn: 67531
* Add a new bit to SUnit to record whether a node has implicit physregDan Gohman2009-03-231-3/+6
| | | | | | defs, regardless of whether they are actually used. llvm-svn: 67528
* Now that errs() is properly non-buffered, there's no need toDan Gohman2009-03-237-11/+5
| | | | | | explicitly flush it. llvm-svn: 67526
* LoopVR is not CFGOnly.Dan Gohman2009-03-231-1/+1
| | | | llvm-svn: 67524
* Enhance LiveValues to work on PHI operands.Dan Gohman2009-03-231-13/+24
| | | | llvm-svn: 67523
* Correct some comments. Operand numbers start at 0.Dan Gohman2009-03-231-6/+6
| | | | llvm-svn: 67518
* Model inline asm constraint which ties an input to an output register as ↵Evan Cheng2009-03-235-40/+122
| | | | | | machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. llvm-svn: 67512
* Do not fold away subreg_to_reg if the source register has a sub-register ↵Evan Cheng2009-03-231-3/+9
| | | | | | | | | | index. That means the source register is taking a sub-register of a larger register. e.g. On x86 %RAX<def> = ... %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 The first def is defining RAX, not EAX so the top bits were not zero-extended. llvm-svn: 67511
* fix a bug Alexei Svitkine pointed out.Chris Lattner2009-03-231-2/+2
| | | | llvm-svn: 67510
* When we restore signal handlers, restore them back to what theyChris Lattner2009-03-231-8/+30
| | | | | | | were when we came around, not to their default handler. This should fix PR3848 llvm-svn: 67509
* factorize signal registration, part of PR3848.Chris Lattner2009-03-231-10/+23
| | | | llvm-svn: 67508
* Fix a grammaro in a comment that Bill noticed.Dan Gohman2009-03-231-1/+1
| | | | llvm-svn: 67507
* Add comments explaining why there's only one register forDan Gohman2009-03-231-1/+6
| | | | | | i8 return values. llvm-svn: 67502
* Factorize out a concept - no functionality change.Duncan Sands2009-03-213-8/+6
| | | | llvm-svn: 67454
* add a fastpath to ConstantExpr::getBitCast to handle the case when an obviouslyChris Lattner2009-03-211-0/+5
| | | | | | | | | unneeded bitcast is requested. This is common for frontends who just unconditionally cast even if the target is often the right type already. THis prevents going into getFoldedCast which switches on the opcode and does a bunch of other stuff before doing the same opzn. llvm-svn: 67435
* Removed AFGR32 register classBruno Cardoso Lopes2009-03-215-176/+110
| | | | | | Handle odd registers allocation in FGR32. llvm-svn: 67422
* Fix a few more indentation problems and an 80-column violation.Bob Wilson2009-03-201-8/+8
| | | | llvm-svn: 67416
* No functional changes. Fix indentation and whitespace only.Bob Wilson2009-03-201-101/+91
| | | | llvm-svn: 67412
* Fix instcombine to not introduce undefined shifts when merging twoChris Lattner2009-03-201-2/+14
| | | | | | shifts together. This fixes PR3851. llvm-svn: 67411
* Don't load values out of global constants with weakDuncan Sands2009-03-203-6/+8
| | | | | | | | | linkage: the value may be replaced with something different at link time. (Frontends that want to allow values to be loaded out of weak constants can give their constants weak_odr linkage). llvm-svn: 67407
* Simplify this code; use a while instead of an if and a do-while.Dan Gohman2009-03-201-9/+6
| | | | llvm-svn: 67400
* For inline asm output operand that matches an input. Encode the input ↵Evan Cheng2009-03-206-29/+44
| | | | | | operand index in the high bits. llvm-svn: 67387
* Fixed comment for libcalls.Sanjiv Gupta2009-03-201-20/+23
| | | | llvm-svn: 67373
* Fixed build warnings for unused variables.Sanjiv Gupta2009-03-201-3/+0
| | | | llvm-svn: 67372
* Reformatting. Inserted code comments. Cleaned interfaces.Sanjiv Gupta2009-03-202-112/+68
| | | | | | Removed unncessary code. No functionality change. llvm-svn: 67371
* Fixed the comment. No functionality change.Sanjiv Gupta2009-03-201-4/+4
| | | | llvm-svn: 67370
* Apply the patch requested in PR3846.Chris Lattner2009-03-201-1/+1
| | | | llvm-svn: 67364
* Added option to enable generating less precise mad (multiply addition)Mon P Wang2009-03-201-0/+12
| | | | | | for those architectures that support the instruction. llvm-svn: 67363
* The last use in a block that doesn't have successorsDan Gohman2009-03-201-0/+5
| | | | | | (return or unreachable) is a kill. llvm-svn: 67357
* Fix the Win32 VS2008 build:Sebastian Redl2009-03-194-12/+15
| | | | | | | | | | - Make type declarations match the struct/class keyword of the definition. - Move AddSignalHandler into the namespace where it belongs. - Correctly call functions from template base. - Some other small changes. With this patch, LLVM and Clang should build properly and with far less noise under VS2008. llvm-svn: 67347
* Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.Evan Cheng2009-03-195-24/+37
| | | | llvm-svn: 67335
* Clear the cached cost when removing a function inDale Johannesen2009-03-193-11/+19
| | | | | | | | | the inliner; prevents nondeterministic behavior when the same address is reallocated. Don't build call graph nodes for debug intrinsic calls; they're useless, and there were typically a lot of them. llvm-svn: 67311
* Add a liveness analysis pass for LLVM IR values. This computesDan Gohman2009-03-191-0/+177
| | | | | | | | | the set of blocks in which values are used, the set in which values are live-through, and the set in which values are killed. For the live-through and killed sets, conservative approximations are used. llvm-svn: 67309
* Fix comment typo.Dale Johannesen2009-03-191-1/+1
| | | | llvm-svn: 67307
* This pass keeps a map of Instructions to Rank numbers,Dale Johannesen2009-03-191-8/+14
| | | | | | | | | and was deleting Instructions without clearing the corresponding map entry. This led to nondeterministic behavior if the same address got allocated to another Instruction within a short time. llvm-svn: 67306
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