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| author | Chris Lattner <sabre@nondot.org> | 2009-03-24 15:27:37 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2009-03-24 15:27:37 +0000 |
| commit | c35847e1094f041c4f3faf40c8d1ad00bff19cd5 (patch) | |
| tree | 18f7b22d77cccf76571f94162fbea265142063cb /llvm/lib | |
| parent | 42eceb349111e532608c801c3a0d719156df2798 (diff) | |
| download | bcm5719-llvm-c35847e1094f041c4f3faf40c8d1ad00bff19cd5.tar.gz bcm5719-llvm-c35847e1094f041c4f3faf40c8d1ad00bff19cd5.zip | |
more tidying: name the components of PhysReg in the case when
the target constraint specifies a specific physreg.
llvm-svn: 67618
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 0f5cc17d8d1..8457bc35f50 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -4896,28 +4896,29 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // If this is a constraint for a specific physical register, like {r17}, // assign it now. - if (PhysReg.first) { + if (unsigned AssignedReg = PhysReg.first) { + const TargetRegisterClass *RC = PhysReg.second; if (OpInfo.ConstraintVT == MVT::Other) - ValueVT = *PhysReg.second->vt_begin(); + ValueVT = *RC->vt_begin(); // Get the actual register value type. This is important, because the user // may have asked for (e.g.) the AX register in i32 type. We need to // remember that AX is actually i16 to get the right extension. - RegVT = *PhysReg.second->vt_begin(); + RegVT = *RC->vt_begin(); // This is a explicit reference to a physical register. - Regs.push_back(PhysReg.first); + Regs.push_back(AssignedReg); // If this is an expanded reference, add the rest of the regs to Regs. if (NumRegs != 1) { - TargetRegisterClass::iterator I = PhysReg.second->begin(); - for (; *I != PhysReg.first; ++I) - assert(I != PhysReg.second->end() && "Didn't find reg!"); + TargetRegisterClass::iterator I = RC->begin(); + for (; *I != AssignedReg; ++I) + assert(I != RC->end() && "Didn't find reg!"); // Already added the first reg. --NumRegs; ++I; for (; NumRegs; --NumRegs, ++I) { - assert(I != PhysReg.second->end() && "Ran out of registers to allocate!"); + assert(I != RC->end() && "Ran out of registers to allocate!"); Regs.push_back(*I); } } |

