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* Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.Craig Topper2011-10-071-0/+23
| | | | llvm-svn: 141358
* PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick2011-10-072-1/+3
| | | | | | Fixes <rdar://problem/10235725> llvm-svn: 141357
* whitespaceAndrew Trick2011-10-072-3/+3
| | | | llvm-svn: 141356
* Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.Craig Topper2011-10-071-0/+15
| | | | llvm-svn: 141354
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-072-21/+16
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
* Use the correct vreg here.Bill Wendling2011-10-061-1/+1
| | | | llvm-svn: 141342
* Generate the dispatch code for a 'thumb' function. This is very similar to theBill Wendling2011-10-061-2/+53
| | | | | | | others. They take the call site value. Determine if it's a proper value. And then jumps to the correct call site via a jump table. llvm-svn: 141341
* Fix the check for nested IT instructions in the disassembler. We need to ↵Owen Anderson2011-10-061-3/+6
| | | | | | perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. llvm-svn: 141339
* Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman2011-10-066-189/+92
| | | | | | with this patch. llvm-svn: 141333
* Generate the dispatch table for ARM mode.Bill Wendling2011-10-061-29/+71
| | | | llvm-svn: 141327
* Refactor some of the code that sets up the entry block for SjLj EH. No ↵Bill Wendling2011-10-062-79/+105
| | | | | | functionality change. llvm-svn: 141323
* Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)Bill Wendling2011-10-061-7/+12
| | | | | | Place the immediate to OR into a register so that it works. llvm-svn: 141319
* * Set the low bit of the return address when we are in thumb mode.Bill Wendling2011-10-061-73/+90
| | | | | | * Some code cleanup. llvm-svn: 141317
* Fix List-of-List ProcessingDavid Greene2011-10-061-1/+3
| | | | | | | | | Fix VarListElementInit::resolveListElementReference to return a partially resolved VarListElementInint in the case where full resolution is not possible. This allows TableGen to make forward progress resolving certain complex list expressions. llvm-svn: 141315
* Fix -asserts buildMatt Beaumont-Gay2011-10-061-0/+2
| | | | llvm-svn: 141313
* PTX: Implement signed divisionJustin Holewinski2011-10-061-5/+34
| | | | llvm-svn: 141306
* Use StringSwitch.Benjamin Kramer2011-10-061-19/+21
| | | | llvm-svn: 141305
* Simplify code. No functionality change.Benjamin Kramer2011-10-061-26/+24
| | | | llvm-svn: 141299
* Fix TypoDavid Greene2011-10-061-1/+1
| | | | | | Compare the entire keyword string. llvm-svn: 141295
* Don't require C bindings opcode numbers to be kept in sync.Torok Edwin2011-10-061-3/+28
| | | | | | | | They are not in sync now, for example Bitcast would show up as LLVMCall. So instead introduce 2 functions that map to and from the opcodes in the C bindings. llvm-svn: 141290
* ocaml/C bindings: type->isSized()Torok Edwin2011-10-061-0/+5
| | | | llvm-svn: 141288
* add binding to read icmp predicateTorok Edwin2011-10-061-0/+9
| | | | llvm-svn: 141287
* ocaml/C bindings: getmdstring, add num_op, get_op should work on metadata tooTorok Edwin2011-10-061-2/+34
| | | | llvm-svn: 141286
* C/OCaml API to retrieve struct name.Torok Edwin2011-10-061-0/+8
| | | | llvm-svn: 141285
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-062-3/+25
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. llvm-svn: 141274
* Build system infrastructure for multiple tblgens.Peter Collingbourne2011-10-0614-99/+99
| | | | llvm-svn: 141266
* Add the MBBs before inserting the instructions. Doing it afterwards could leadBill Wendling2011-10-061-28/+10
| | | | | | | | to an infinite loop because of the def-use chains. Also use a frame load instead of store for the LD instruction. llvm-svn: 141263
* Always merge profitable shifts on A9, not just when they have a single use.Cameron Zwarich2011-10-051-6/+2
| | | | llvm-svn: 141248
* Remove a check from ARM shifted operand isel helper methods, which were blockingCameron Zwarich2011-10-051-10/+0
| | | | | | | | merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. llvm-svn: 141247
* Get the proper call site numbers for the landing pads. Also remove a magicBill Wendling2011-10-051-15/+27
| | | | | | number (18) for the proper addressing mode. llvm-svn: 141245
* Prefix Template Arg Names with Multiclass NameDavid Greene2011-10-051-0/+3
| | | | | | | | For consistency, prefix multiclass template arg names with the multiclass name followed by "::" to avoid name clashes among multiclass arguments and other entities in the multiclass. llvm-svn: 141239
* Process MultidefsDavid Greene2011-10-051-0/+86
| | | | | | | | | | Process each multidef declared in a multiclass. Iterate through the list and instantiate a def in the multiclass for each item, resolving the list item to the temporary iterator (possibly) used in the multidef ObjectBody. We then process each generated def in the normal way. llvm-svn: 141233
* Parser Multidef SupportDavid Greene2011-10-052-1/+89
| | | | | | | | | | | | | | | Add parser support to recognize multidefs. No processing on the multidef is done at this point. The grammar is: MultiDef = MULTIDEF ObjectName < Value, Declaration, Value > ObjectBody The first Value must be resolveable to a list and the second Value must be resolveable to an integer. The Declaration is a temporary value used as an iterator to refer to list items during processing. It may be passed into the ObjectBody where it will be substituted with the list value used to instantiate each def. llvm-svn: 141232
* Lexer Support for MultidefsDavid Greene2011-10-052-1/+2
| | | | | | Add keyword support for multidefs. llvm-svn: 141231
* Refactor Multiclass Def ProcessingDavid Greene2011-10-052-87/+131
| | | | | | | | Move the code to instantiate a multiclass def, bind its arguments and resolve its members into three helper functions. These will be reused to support a new kind of multiclass def: a multidef. llvm-svn: 141229
* PR11061: Make simplifylibcalls fold strcmp("", x) correctly.Eli Friedman2011-10-051-13/+18
| | | | | | While I'm here, fix the related issue with strncmp, add some actual tests for strcmp and strncmp, and start using StringRef::compare for constant folding instead of using strcmp/strncmp so that the optimized IR isn't dependent on the host's implementation of strcmp. llvm-svn: 141227
* Modify the mapping from landing pad to call sites to accept more than one callBill Wendling2011-10-053-3/+6
| | | | | | site. llvm-svn: 141226
* Add an ivar that maps a landing pad's EH symbol to the call sites that may jumpBill Wendling2011-10-051-0/+8
| | | | | | | to the landing pad. This will be used by the back-end to generate the jump tables for dispatching the arriving longjmp in sjlj eh. llvm-svn: 141224
* Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling2011-10-051-7/+7
| | | | llvm-svn: 141221
* Fix sub-register operand verification.Jakob Stoklund Olesen2011-10-051-12/+25
| | | | | | | | | PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. llvm-svn: 141220
* Fixes PR11070 - assert in SCEV getConstantEvolvingPHIOperands.Andrew Trick2011-10-051-16/+10
| | | | llvm-svn: 141219
* Fix comment to reflect the new EH stuff.Bill Wendling2011-10-051-1/+1
| | | | llvm-svn: 141218
* Remove unused DstSubIdx argument.Jakob Stoklund Olesen2011-10-051-23/+5
| | | | llvm-svn: 141214
* Re-commit 141203, but much more conservative.Jim Grosbach2011-10-051-3/+3
| | | | | | | | Just pull the instruction name, but don't change the order of anything else. That keeps --debug happy and non-crashing, but doesn't change how the worklist gets built. llvm-svn: 141210
* Revert 141203. InstCombine is looping on unit tests.Jim Grosbach2011-10-051-9/+8
| | | | llvm-svn: 141209
* Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen2011-10-052-27/+52
| | | | | | | | | | | | EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. llvm-svn: 141207
* Override TRI::getSubClassWithSubReg for X86.Jakob Stoklund Olesen2011-10-052-0/+15
| | | | | | | | There are fewer registers with sub_8bit sub-registers in 32-bit mode than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as sub_8bit_hi. llvm-svn: 141206
* Check for the returns_twice attribute in callsFunctionThatReturnsTwice. ThisRafael Espindola2011-10-051-10/+19
| | | | | | fixes PR11038, but there are still some cleanups to be done. llvm-svn: 141204
* Update InstCombine worklist after instruction transform is complete.Jim Grosbach2011-10-051-8/+9
| | | | | | | | | | | | When updating the worklist for InstCombine, the Add/AddUsersToWorklist functions may access the instruction(s) being added, for debug output for example. If the instructions aren't yet added to the basic block, this can result in a crash. Finish the instruction transformation before adjusting the worklist instead. rdar://10238555 llvm-svn: 141203
* PTX: Fixup a case where getRegClassFor() should be used instead of custom code.Justin Holewinski2011-10-051-17/+1
| | | | llvm-svn: 141199
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