summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorOwen Anderson <resistor@mac.com>2011-10-06 23:33:11 +0000
committerOwen Anderson <resistor@mac.com>2011-10-06 23:33:11 +0000
commit6a5c150e9cefdf2368ac4f6a45cc7d914887ed10 (patch)
tree594c9c6d6426d15c9d4833ac62cdd4a550fdbdb6 /llvm/lib
parent70a11261ac9ef8e84267a9a84acc391de17a0ada (diff)
downloadbcm5719-llvm-6a5c150e9cefdf2368ac4f6a45cc7d914887ed10.tar.gz
bcm5719-llvm-6a5c150e9cefdf2368ac4f6a45cc7d914887ed10.zip
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
llvm-svn: 141339
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp9
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 36aa6b10ee4..5f6fc29b089 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -724,15 +724,18 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 2;
+
+ // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
+ // the Thumb predicate.
+ if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
+ result = MCDisassembler::SoftFail;
+
Check(result, AddThumbPredicate(MI));
// If we find an IT instruction, we need to parse its condition
// code and mask operands so that we can apply them correctly
// to the subsequent instructions.
if (MI.getOpcode() == ARM::t2IT) {
- // Nested IT blocks are UNPREDICTABLE.
- if (!ITBlock.empty())
- return MCDisassembler::SoftFail;
// (3 - the number of trailing zeros) is the number of then / else.
unsigned firstcond = MI.getOperand(0).getImm();
OpenPOWER on IntegriCloud