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* Spill and restore PPC CR registers using the FP when we have oneHal Finkel2013-04-131-6/+14
| | | | | | | | | | For functions that need to spill CRs, and have dynamic stack allocations, the value of the SP during the restore is not what it was during the save, and so we need to use the FP in these cases (as for all of the other spills and restores, but the CR restore has a special code path because its reserved slot, like the link register, is specified directly relative to the adjusted SP). llvm-svn: 179457
* MI-Sched: DEBUG formatting.Andrew Trick2013-04-131-14/+22
| | | | llvm-svn: 179452
* MI-Sched cleanup. If an instruction has no valid sched class, do not attempt ↵Andrew Trick2013-04-131-0/+2
| | | | | | to check for a variant. llvm-svn: 179451
* X86 machine model: reduce SandyBridge and Haswell ILPWindow.Andrew Trick2013-04-132-2/+2
| | | | | | | | | | | | | | | The initial values were arbitrary. I want them to be more conservative. This represents the number of latency cycles hidden by OOO execution. In practice, I think it should be within a small factor of the complex floating point operation latency so the scheduler can make some attempt to hide latency even for smallish blocks. These are by no means the best values, just a starting point for tuning heuristics. Some benchmarks such as TSVC run faster with this lower value for SandyBridge. I haven't run anything on Haswell, but it's shouldn't be 2x SB. llvm-svn: 179450
* MI-Sched: schedule physreg copies.Andrew Trick2013-04-132-1/+76
| | | | | | | | | | | The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. llvm-svn: 179449
* Catch another case where SD fails to propagate node order.Andrew Trick2013-04-131-1/+4
| | | | | | | | | | I need to handle this for the test case in my following scheduler commit. Work is already under way to redesign the mechanism for node order propagation because this case by case approach is unmaintainable. llvm-svn: 179448
* [mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN andAkira Hatanaka2013-04-134-172/+174
| | | | | | | | lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
* Finish templating MachObjectFile over endianness.Rafael Espindola2013-04-131-417/+15
| | | | | | | We are now able to handle big endian macho files in llvm-readobject. Thanks to David Fang for providing the object files. llvm-svn: 179440
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-134-11/+41
| | | | llvm-svn: 179434
* [mips] Override TargetLoweringBase::isShuffleMaskLegal.Akira Hatanaka2013-04-131-0/+5
| | | | llvm-svn: 179433
* [ms-inline asm] Simplify the logic by using parsePrimaryExpr. No functionalChad Rosier2013-04-121-1/+1
| | | | | | | change intended. Test case previously added in r178568. Part of rdar://13611297 llvm-svn: 179425
* Revert r179420 and r179421.Akira Hatanaka2013-04-124-41/+11
| | | | llvm-svn: 179422
* [mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka2013-04-123-6/+15
| | | | | | instructions. llvm-svn: 179421
* [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka2013-04-122-5/+26
| | | | llvm-svn: 179420
* Revert r179409 because it caused some warnings and some of the build bots fail.Nadav Rotem2013-04-121-277/+44
| | | | llvm-svn: 179418
* InstCombine: Check the operand types before merging fcmp ord & fcmp ord.Benjamin Kramer2013-04-121-0/+3
| | | | | | Fixes PR15737. llvm-svn: 179417
* SLPVectorizer: add support for vectorization of diamond shaped trees. We now ↵Nadav Rotem2013-04-122-46/+254
| | | | | | perform a preliminary traversal of the graph to collect values with multiple users and check where the users came from. llvm-svn: 179414
* CostModel: increase the default cost of supported floating point operations ↵Nadav Rotem2013-04-121-4/+7
| | | | | | from 1 to two. Fixed a few tests that changes because now the cost of one insert + a vector operation on two doubles is lower than two scalar operations on doubles. llvm-svn: 179413
* Add debug prints.Nadav Rotem2013-04-121-1/+5
| | | | llvm-svn: 179412
* Add support for additional vector instructions in the interpreter.Nadav Rotem2013-04-121-44/+277
| | | | | | patch by Veselov, Yuri <Yuri.Veselov@intel.com>. llvm-svn: 179409
* [ms-inline asm] Move this logic into a static function as it's only applicableChad Rosier2013-04-121-63/+67
| | | | | | when parsing MS-style inline assembly. No functional change intended. llvm-svn: 179407
* [ms-inline asm] Address the FIXME for ImmDisp before brackets. ThisChad Rosier2013-04-121-18/+29
| | | | | | | | is a follow on to r179393 and r179399. Test case to be added on the clang side. Part of rdar://13453209 llvm-svn: 179403
* [ms-inline asm] Have the [ Symbol ] case fall into the more general logic. ThisChad Rosier2013-04-121-46/+24
| | | | | | | is a follow on to r179393. Test case to be added on the clang side. Part of rdar://13453209 llvm-svn: 179399
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-124-26/+57
| | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
* [ms-inline asm] Add support for operands that include both a symbol and anChad Rosier2013-04-121-41/+103
| | | | | | | | | immediate displacement. Specifically, add support for generating the proper IR. We've been able to parse this for some time now. Test case to be added on the clang side. Part of rdar://13453209 llvm-svn: 179393
* PPC: Remove (broken) nested implicit definition listsHal Finkel2013-04-122-94/+153
| | | | | | | | | | TableGen will not combine nested list 'let' bindings into a single list, and instead uses only the inner scope. As a result, several instruction definitions were missing implicit register defs that were in outer scopes. This de-nests these scopes and makes all instructions have only one let binding which sets implicit register definitions. llvm-svn: 179392
* Add a comment about the PPC Interpretation64Bit bitHal Finkel2013-04-121-0/+5
| | | | llvm-svn: 179391
* Hexagon: Set isPredicatedNew flag on predicate new instructions.Jyotsna Verma2013-04-122-22/+21
| | | | llvm-svn: 179388
* Hexagon: Set isPredicatedFlase flag for all the instructions with negated ↵Jyotsna Verma2013-04-122-21/+21
| | | | | | predication. llvm-svn: 179387
* Simplify (A & ~B) in icmp if A is a power of 2David Majnemer2013-04-121-0/+9
| | | | | | | | The transform will execute like so: (A & ~B) == 0 --> (A & B) != 0 (A & ~B) != 0 --> (A & B) == 0 llvm-svn: 179386
* [ms-inline asm] Add the implementation for the AOK_Delete kind, which was addedChad Rosier2013-04-121-3/+5
| | | | | | | in r179325. Test case coming shortly on the clang side. Part of rdar://13453209 llvm-svn: 179383
* LoopVectorizer: integer division is not a reduction operationArnold Schwaighofer2013-04-121-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't classify idiv/udiv as a reduction operation. Integer division is lossy. For example : (1 / 2) * 4 != 4/2. Example: int a[] = { 2, 5, 2, 2} int x = 80; for() x /= a[i]; Scalar: x /= 2 // = 40 x /= 5 // = 8 x /= 2 // = 4 x /= 2 // = 2 Vectorized: <80, 1> / <2,5> //= <40,0> <40, 0> / <2,2> //= <20,0> 20*0 = 0 radar://13640654 llvm-svn: 179381
* Revert broken pieces of r179373.Benjamin Kramer2013-04-121-16/+16
| | | | | | You can't copy an OwningPtr, and move semantics aren't available in C++98. llvm-svn: 179374
* Replace uses of the deprecated std::auto_ptr with OwningPtr.Andy Gibbs2013-04-123-20/+20
| | | | llvm-svn: 179373
* Fix a disconcerting bug in Value::isUsedInBasicBlock, which gave wrong ↵Benjamin Kramer2013-04-121-1/+1
| | | | | | | | answers for blocks larger than 3 instrs. Also add a unit test. PR15727. llvm-svn: 179370
* Add PPC instruction record forms and associated query functionsHal Finkel2013-04-125-416/+670
| | | | | | | | | | | | | | | | | | This is prep. work for the implementation of optimizeCompare. Many PPC instructions have 'record' forms (in almost all cases, this means that the RC bit is set) that cause the result of the instruction to be compared with zero, and the result of that comparison saved in a predefined condition register. In order to add the record forms of the instructions without too much copy-and-paste, the relevant functions have been refactored into multiclasses which define both the record and normal forms. Also, two TableGen-generated mapping functions have been added which allow querying the instruction code for the record form given the normal form (and vice versa). No functionality change intended. llvm-svn: 179356
* Don't disable block layout when forcing block alignment.Nadav Rotem2013-04-121-8/+6
| | | | llvm-svn: 179355
* Add a flag to align all basic blocks in the function.Nadav Rotem2013-04-121-0/+14
| | | | | | | | | | When debugging performance regressions we often ask ourselves if the regression that we see is due to poor isel/sched/ra or due to some micro-architetural problem. When comparing two code sequences one good way to rule out front-end bottlenecks (and other the issues) is to force code alignment. This pass adds a flag that forces the alignment of all of the basic blocks in the program. llvm-svn: 179353
* Add 179294 back, but don't use bit fields so that it works on big endian hosts.Rafael Espindola2013-04-121-8/+44
| | | | | | | | | | | | | | Original message: Print more information about relocations. With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. llvm-svn: 179345
* [ms-inline asm] Add support for using the LENGTH, TYPE, and SIZE operators withChad Rosier2013-04-111-2/+11
| | | | | | | | variables that use namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 llvm-svn: 179343
* [ms-inline asm] Add support for using offsetof operator with variables that useChad Rosier2013-04-111-3/+6
| | | | | | | namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 llvm-svn: 179339
* Aliasing rules for struct-path aware TBAA.Manman Ren2013-04-111-0/+136
| | | | | | | Added PathAliases to check if two struct-path tags can alias. Added command line option -struct-path-tbaa. llvm-svn: 179337
* [ms-inline asm] Pass a StringRef reference to ParseIntelVarWithQualifier so weChad Rosier2013-04-111-15/+15
| | | | | | | | can build up the identifier string. No test case as support for looking up these type of identifiers hasn't been implemented on the clang side. Part of rdar://13499009 llvm-svn: 179336
* [ms-inline asm] Remove brackets from around a symbol reference in the targetChad Rosier2013-04-112-10/+11
| | | | | | | | specific logic. This makes the code much less fragile. Test case coming on the clang side in a moment. rdar://13634327 llvm-svn: 179323
* Fix undefined behavior in AArch64David Majnemer2013-04-111-7/+11
| | | | | | | | A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to execute shifts that perform undefined behavior. Instead of attempting to perform the 64-bit rotation, treat it as a no-op. llvm-svn: 179317
* Optimize icmp involving addition betterDavid Majnemer2013-04-111-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Allows LLVM to optimize sequences like the following: %add = add nsw i32 %x, 1 %cmp = icmp sgt i32 %add, %y into: %cmp = icmp sge i32 %x, %y as well as: %add1 = add nsw i32 %x, 20 %add2 = add nsw i32 %y, 57 %cmp = icmp sge i32 %add1, %add2 into: %add = add nsw i32 %y, 37 %cmp = icmp sle i32 %cmp, %x llvm-svn: 179316
* [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selectsAkira Hatanaka2013-04-112-64/+4
| | | | | | | | multiply instructions in MipsSEDAGToDAGISel. This patch was supposed to be part of r178403. llvm-svn: 179314
* [mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.Akira Hatanaka2013-04-113-13/+12
| | | | | | | | | | - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
* Revert my last two commits while I debug what is wrong in a big endian host.Rafael Espindola2013-04-111-44/+8
| | | | llvm-svn: 179303
* Print more information about relocations.Rafael Espindola2013-04-111-8/+44
| | | | | | | | | | With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. llvm-svn: 179294
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