summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [MCJIT] Fix some inconsistent handling of name mangling inside MCJIT.Lang Hames2016-09-122-12/+21
| | | | | | | | | | | This patch moves symbol mangling from findSymbol to getSymbolAddress. The findSymbol, findExistingSymbol and findModuleForSymbol methods now always take a mangled name, allowing the 'demangle-and-retry' cruft to be removed from findSymbol. See http://llvm.org/PR28699 for details. Patch by James Holderness. Thanks very much James! llvm-svn: 281238
* [InstCombine] use m_APInt to allow icmp X, C folds for splat constant vectorsSanjay Patel2016-09-121-2/+3
| | | | | | isSignBitCheck could be changed to take a pointer param to avoid the 'UnusedBit' ugliness. llvm-svn: 281231
* AMDGPU: Do not clobber SCC in SIWholeQuadModeNicolai Haehnle2016-09-122-75/+210
| | | | | | | | | | Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D22198 llvm-svn: 281230
* [GlobalISel] Fix mismatched "<..)" in intrinsic MO printing. NFC.Ahmed Bougacha2016-09-121-2/+2
| | | | llvm-svn: 281229
* Revert "[ARM] Promote small global constants to constant pools"James Molloy2016-09-124-123/+1
| | | | | | This reverts commit r281213. It made a bot go bang: http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-full/builds/14625 llvm-svn: 281228
* [BranchFolding] Unique added live-ins after hoisting code.Ahmed Bougacha2016-09-121-0/+7
| | | | | | We're not supposed to have duplicate live-ins. llvm-svn: 281224
* [X86] Copy imp-uses when folding tailcall into conditional branch.Ahmed Bougacha2016-09-121-1/+1
| | | | | | | | | | | r280832 added 32-bit support for emitting conditional tail-calls, but dropped imp-used parameter registers. This went unnoticed until r281113, which added 64-bit support, as this is only exposed with parameter passing via registers. Don't drop the imp-used parameters. llvm-svn: 281223
* [FunctionAttrs] Don't try to infer returned if it is already on an argumentDavid Majnemer2016-09-121-0/+5
| | | | | | | | | | | Trying to infer the 'returned' attribute if an argument is already 'returned' can lead to verification failure: inference might determine that a different argument is passed through which would result in two different arguments marked as 'returned'. This fixes PR30350. llvm-svn: 281221
* fix formatting; NFCSanjay Patel2016-09-121-14/+13
| | | | llvm-svn: 281220
* [InstCombine] add helper function for foldICmpUsingKnownBits; NFCISanjay Patel2016-09-122-259/+279
| | | | llvm-svn: 281217
* [AMDGPU] Assembler: Move disabled SDWA and DPP instruction into Disable asm ↵Sam Kolton2016-09-122-0/+12
| | | | | | | | | | | | | | variant Summary: This removes disabled instructions from match tables so we will not match them at all. Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: wdng, nhaehnle, arsenm Differential Revision: https://reviews.llvm.org/D24452 llvm-svn: 281216
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-09-122-5/+139
| | | | | | | | | | | | | For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)). 1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS. 2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS. 3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS). 4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask. 1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win. llvm-svn: 281215
* fix formatting/typos; NFCSanjay Patel2016-09-122-12/+11
| | | | llvm-svn: 281214
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-124-1/+123
| | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). llvm-svn: 281213
* [LoopInterchange] Improve debug output. NFC.Chad Rosier2016-09-121-2/+2
| | | | llvm-svn: 281212
* Define a dummy zlib::uncompress when zlib is not available.Rafael Espindola2016-09-121-0/+4
| | | | | | Should fix link errors in some bots when it is used. llvm-svn: 281208
* GlobalISel: support translation of global addresses.Tim Northover2016-09-122-0/+14
| | | | llvm-svn: 281207
* GlobalISel: translate GEP instructions.Tim Northover2016-09-122-0/+95
| | | | | | | | Unlike SDag, we use a separate G_GEP instruction (much simplified, only taking a single byte offset) to preserve the pointer type information through selection. llvm-svn: 281205
* GlobalISel: disambiguate types when printing MIRTim Northover2016-09-124-19/+56
| | | | | | | | | | | | | | | | | Some generic instructions have multiple types. While in theory these always be discovered by inspecting the single definition of each generic vreg, in practice those definitions won't always be local and traipsing through a big function to find them will not be fun. So this changes MIRPrinter to print out the type of uses as well as defs, if they're known to be different or not known to be the same. On the parsing side, we're a little more flexible: provided each register is given a type in at least one place it's mentioned (and all types are consistent) we accept the MIR. This doesn't introduce ambiguity but makes writing tests manually a bit less painful. llvm-svn: 281204
* Fix WebAssembly broken build related to interface change in r281172.Eric Liu2016-09-121-2/+1
| | | | | | | | | | Reviewers: bkramer Subscribers: jfb, llvm-commits, dschuff Differential Revision: https://reviews.llvm.org/D24449 llvm-svn: 281201
* MC: Move MCSection::begin/end to header, NFCDuncan P. N. Exon Smith2016-09-121-8/+0
| | | | llvm-svn: 281188
* [InstCombine] add helper function for folding {and,or,xor} (cast X), C ; NFCISanjay Patel2016-09-121-28/+41
| | | | llvm-svn: 281187
* ADT: Add AllocatorList, and use it for yaml::TokenDuncan P. N. Exon Smith2016-09-111-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add AllocatorList, a non-intrusive list that owns an LLVM-style allocator and provides a std::list-like interface (trivially built on top of simple_ilist), - add a typedef (and unit tests) for BumpPtrList, and - use BumpPtrList for the list of llvm::yaml::Token (i.e., TokenQueueT). TokenQueueT has no need for the complexity of an intrusive list. The only reason to inherit from ilist was to customize the allocator. TokenQueueT was the only example in-tree of using ilist<> in a truly non-intrusive way. Moreover, this removes the final use of the non-intrusive ilist_traits<>::createNode (after r280573, r281177, and r281181). I have a WIP patch that removes this customization point (and the API that relies on it) that I plan to commit soon. Note: AllocatorList owns the allocator, which limits the viable API (e.g., splicing must be on the same list). For now I've left out any problematic API. It wouldn't be hard to split AllocatorList into two layers: an Impl class that calls DerivedT::getAlloc (via CRTP), and derived classes that handle Allocator ownership/reference/etc semantics; and then implement splice with appropriate assertions; but TBH we should probably just customize the std::list allocators at that point. llvm-svn: 281182
* [TwoAddressInstruction] When commuting an instruction don't assume that the ↵Craig Topper2016-09-111-3/+5
| | | | | | | | destination register is operand 0. Pass it from the caller. In practice it probably is 0 so this may not be a functional change. llvm-svn: 281180
* ScalarOpts: Use std::list for Candidates, NFCDuncan P. N. Exon Smith2016-09-111-2/+3
| | | | | | | There is nothing intrusive about the Candidate list; use std::list over llvm::ilist for simplicity. llvm-svn: 281177
* ScalarOpts: Sort includes, NFCDuncan P. N. Exon Smith2016-09-111-2/+1
| | | | llvm-svn: 281176
* CodeGen: Give MachineBasicBlock::reverse_iterator a handle to the current MIDuncan P. N. Exon Smith2016-09-1111-51/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that MachineBasicBlock::reverse_instr_iterator knows when it's at the end (since r281168 and r281170), implement MachineBasicBlock::reverse_iterator directly on top of an ilist::reverse_iterator by adding an IsReverse template parameter to MachineInstrBundleIterator. This replaces another hard-to-reason-about use of std::reverse_iterator on list iterators, matching the changes for ilist::reverse_iterator from r280032 (see the "out of scope" section at the end of that commit message). MachineBasicBlock::reverse_iterator now has a handle to the current node and has obvious invalidation semantics. r280032 has a more detailed explanation of how list-style reverse iterators (invalidated when the pointed-at node is deleted) are different from vector-style reverse iterators like std::reverse_iterator (invalidated on every operation). A great motivating example is this commit's changes to lib/CodeGen/DeadMachineInstructionElim.cpp. Note: If your out-of-tree backend deletes instructions while iterating on a MachineBasicBlock::reverse_iterator or converts between MachineBasicBlock::iterator and MachineBasicBlock::reverse_iterator, you'll need to update your code in similar ways to r280032. The following table might help: [Old] ==> [New] delete &*RI, RE = end() delete &*RI++ RI->erase(), RE = end() RI++->erase() reverse_iterator(I) std::prev(I).getReverse() reverse_iterator(I) ++I.getReverse() --reverse_iterator(I) I.getReverse() reverse_iterator(std::next(I)) I.getReverse() RI.base() std::prev(RI).getReverse() RI.base() ++RI.getReverse() --RI.base() RI.getReverse() std::next(RI).base() RI.getReverse() (For more details, have a look at r280032.) llvm-svn: 281172
* CodeGen: Turn on sentinel tracking for MachineInstr iteratorsDuncan P. N. Exon Smith2016-09-111-3/+3
| | | | | | | | | | | | | | | | | | | | This is a prep commit before fixing MachineBasicBlock::reverse_iterator invalidation semantics, ala r281167 for ilist::reverse_iterator. This changes MachineBasicBlock::Instructions to track which node is the sentinel regardless of LLVM_ENABLE_ABI_BREAKING_CHECKS. There's almost no functionality change (aside from ABI). However, in the rare configuration: #if !defined(NDEBUG) && !defined(LLVM_ENABLE_ABI_BREAKING_CHECKS) the isKnownSentinel() assertions in ilist_iterator<>::operator* suddenly have teeth for MachineInstr. If these assertions start firing for your out-of-tree backend, have a look at the suggestions in the commit message for r279314, and at some of the commits leading up to it that avoid dereferencing the end() iterator. llvm-svn: 281168
* [AVX512] Fix pattern for vgetmantsd and all other instructions that use same ↵Igor Breger2016-09-111-8/+1
| | | | | | | | class. Fix memory operand size, remove unnecessary pattern. Differential Revision: http://reviews.llvm.org/D24443 llvm-svn: 281164
* [SimplifyCFG] Be even more conservative in SinkThenElseCodeToEndJames Molloy2016-09-111-15/+19
| | | | | | | | This should *actually* fix PR30244. This cranks up the workaround for PR30188 so that we never sink loads or stores of allocas. The idea is that these should be removed by SROA/Mem2Reg, and any movement of them may well confuse SROA or just cause unwanted code churn. It's not ideal that the midend should be crippled like this, but that unwanted churn can really cause significant regressions in important workloads (tsan). llvm-svn: 281162
* [SimplifyCFG] Harden up the profitability heuristic for block splitting ↵James Molloy2016-09-111-5/+20
| | | | | | | | | | | | during sinking Exposed by PR30244, we will split a block currently if we think we can sink at least one instruction. However this isn't right - the reason we split predecessors is so that we can sink instructions that otherwise couldn't be sunk because it isn't safe to do so - stores, for example. So, change the heuristic to only split if it thinks it can sink at least one non-speculatable instruction. Should fix PR30244. llvm-svn: 281160
* [CodeGen] Make the TwoAddressInstructionPass check if the instruction is ↵Craig Topper2016-09-111-1/+4
| | | | | | commutable before calling findCommutedOpIndices for every operand. Also make sure the operand is a register before each call to save some work on commutable instructions that might have an operand. llvm-svn: 281158
* [AVX-512] Add VPTERNLOG to load folding tables.Craig Topper2016-09-111-0/+18
| | | | llvm-svn: 281156
* [X86] Make a helper method into a static function local to the cpp file.Craig Topper2016-09-112-11/+10
| | | | llvm-svn: 281154
* Add handling of !invariant.load to PropagateMetadata.Justin Lebar2016-09-111-6/+6
| | | | | | | | | | | | | | Summary: This will let e.g. the load/store vectorizer propagate this metadata appropriately. Reviewers: arsenm Subscribers: tra, jholewinski, hfinkel, mzolotukhin Differential Revision: https://reviews.llvm.org/D23479 llvm-svn: 281153
* [NVPTX] Use ldg for explicitly invariant loads.Justin Lebar2016-09-111-13/+22
| | | | | | | | | | | | | | | | | | Summary: With this change (plus some changes to prevent !invariant from being clobbered within llvm), clang will be able to model the __ldg CUDA builtin as an invariant load, rather than as a target-specific llvm intrinsic. This will let the optimizer play with these loads -- specifically, we should be able to vectorize them in the load-store vectorizer. Reviewers: tra Subscribers: jholewinski, hfinkel, llvm-commits, chandlerc Differential Revision: https://reviews.llvm.org/D23477 llvm-svn: 281152
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-1122-62/+101
| | | | | | | | | | | | | | | | | | | Summary: An IR load can be invariant, dereferenceable, neither, or both. But currently, MI's notion of invariance is IR-invariant && IR-dereferenceable. This patch splits up the notions of invariance and dereferenceability at the MI level. It's NFC, so adds some probably-unnecessary "is-dereferenceable" checks, which we can remove later if desired. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23371 llvm-svn: 281151
* It should also be legal to pass a swifterror parameter to a call as a swifterrorArnold Schwaighofer2016-09-101-4/+9
| | | | | | | | argument. rdar://28233388 llvm-svn: 281147
* InstCombine: Don't combine loads/stores from swifterror to a new typeArnold Schwaighofer2016-09-101-0/+8
| | | | | | | | | This generates invalid IR: the only users of swifterror can be call arguments, loads, and stores. rdar://28242257 llvm-svn: 281144
* Add an isSwiftError predicate to ValueArnold Schwaighofer2016-09-101-0/+10
| | | | llvm-svn: 281143
* [InstCombine] clean up foldICmpBinOpEqualityWithConstant / ↵Sanjay Patel2016-09-101-59/+56
| | | | | | | | | foldICmpIntrinsicWithConstant ; NFC 1. Rename variables to be consistent with related/preceding code (may want to reorganize). 2. Fix comments/formatting. llvm-svn: 281140
* [InstCombine] rename and reorganize some icmp folding functions; NFCSanjay Patel2016-09-102-24/+23
| | | | | | | | | | Everything under foldICmpInstWithConstant() should now be working for splat vectors via m_APInt matchers. Ie, I've removed all of the FIXMEs that I added while cleaning that section up. Note that not all of the associated FIXMEs in the regression tests are gone though, because some of the tests require earlier folds that are still scalar-only. llvm-svn: 281139
* We also need to pass swifterror in R12 under swiftcc not only under cccArnold Schwaighofer2016-09-101-0/+3
| | | | | | rdar://28190687 llvm-svn: 281138
* [AMDGPU] Refactor MUBUF/MTBUF instructionsValery Pykhtin2016-09-106-1168/+1306
| | | | | | Differential revision: https://reviews.llvm.org/D24295 llvm-svn: 281137
* [WebAssembly] Fix typos in commentsHeejin Ahn2016-09-101-11/+14
| | | | llvm-svn: 281131
* [libFuzzer] print a failed-merge warning only in the merge modeKostya Serebryany2016-09-101-0/+1
| | | | llvm-svn: 281130
* AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndexMatt Arsenault2016-09-106-21/+90
| | | | llvm-svn: 281128
* AMDGPU: Fix scheduling info for spill pseudosMatt Arsenault2016-09-101-2/+3
| | | | | | | These defaulted to Write32Bit. I don't think this actually matters since these don't exist during scheduling. llvm-svn: 281127
* [asan] Add flag to allow lifetime analysis of problematic allocasVitaly Buka2016-09-101-0/+6
| | | | | | | | | | | | | | Summary: Could be useful for comparison when we suspect that alloca was skipped because of this. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24437 llvm-svn: 281126
* [CodeGen] Rename MachineInstr::isInvariantLoad to ↵Justin Lebar2016-09-108-16/+16
| | | | | | | | | | | | | | | | | | | | isDereferenceableInvariantLoad. NFC Summary: I want to separate out the notions of invariance and dereferenceability at the MI level, so that they correspond to the equivalent concepts at the IR level. (Currently an MI load is MI-invariant iff it's IR-invariant and IR-dereferenceable.) First step is renaming this function. Reviewers: chandlerc Subscribers: MatzeB, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D23370 llvm-svn: 281125
OpenPOWER on IntegriCloud