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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-10 01:20:28 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-10 01:20:28 +0000 |
| commit | 7348a7eadd0bce8e5bad6339931e6a655fc0007e (patch) | |
| tree | 5412150bf8c020f0942b020e733b1fcef4523ec7 /llvm/lib | |
| parent | 3ac3aa50f6c98a42e50b4265e8fb92cbbe919140 (diff) | |
| download | bcm5719-llvm-7348a7eadd0bce8e5bad6339931e6a655fc0007e.tar.gz bcm5719-llvm-7348a7eadd0bce8e5bad6339931e6a655fc0007e.zip | |
AMDGPU: Fix scheduling info for spill pseudos
These defaulted to Write32Bit. I don't think this actually matters
since these don't exist during scheduling.
llvm-svn: 281127
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index b8f3c10e618..83f0c3e6504 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1365,7 +1365,8 @@ defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>; multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { - let UseNamedOperandTable = 1, VGPRSpill = 1 in { + let UseNamedOperandTable = 1, VGPRSpill = 1, + SchedRW = [WriteVMEM] in { def _SAVE : VPseudoInstSI < (outs), (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc, @@ -1386,7 +1387,7 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { // (2 * 4) + (8 * num_subregs) bytes maximum let Size = !add(!shl(!srl(vgpr_class.Size, 5), 3), 8); } - } // End UseNamedOperandTable = 1, VGPRSpill = 1 + } // End UseNamedOperandTable = 1, VGPRSpill = 1, SchedRW = [WriteVMEM] } defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>; |
