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* Shuffle StandardPasses.cpp into VMCore; add it to CMake.Eli Friedman2011-05-182-0/+1
| | | | llvm-svn: 131600
* Use IRBuilder while simplifying branch.Devang Patel2011-05-181-12/+13
| | | | llvm-svn: 131598
* Revert unintentional commit.Eli Friedman2011-05-181-26/+5
| | | | llvm-svn: 131597
* More instcombine simplifications towards better debug locations.Eli Friedman2011-05-183-18/+36
| | | | llvm-svn: 131596
* Add missing mayLoad / mayStore flags to instruction definitions without ↵Cameron Zwarich2011-05-181-0/+5
| | | | | | | | patterns, which fixes all of the CodeGen/MBlaze verifier failures. llvm-svn: 131595
* Reserve the segment registers on x86 to fix verifier failures in any code thatCameron Zwarich2011-05-181-0/+9
| | | | | | uses them. llvm-svn: 131591
* Remove comments as Chris requested.Charles Davis2011-05-181-48/+12
| | | | llvm-svn: 131590
* Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha.Cameron Zwarich2011-05-181-0/+1
| | | | llvm-svn: 131587
* Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner2011-05-181-1/+2
| | | | | | Add test case. llvm-svn: 131582
* Third pass at allowing plugins to modify default passes. This time with a ↵Eli Friedman2011-05-181-0/+247
| | | | | | tweak so that we don't depend on an uninitialized argument. llvm-svn: 131581
* Use IRBuilder while simplifying return instruction.Devang Patel2011-05-181-11/+13
| | | | llvm-svn: 131580
* Fix an obvious typo in r131572.Cameron Zwarich2011-05-181-2/+2
| | | | llvm-svn: 131579
* Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing ↵Cameron Zwarich2011-05-181-4/+7
| | | | | | turned on. llvm-svn: 131578
* When forming an ICmpZero LSRUse, normalize the non-IV operandDan Gohman2011-05-181-0/+4
| | | | | | | of the comparison, so that the resulting expression is fully normalized. This fixes PR9939. llvm-svn: 131576
* Add some more Win64 EH directives:Charles Davis2011-05-182-0/+60
| | | | | | | | | | | | | - StartChained and EndChained delimit a chained unwind area, which can contain additional operations to be undone if an exception occurs inside of it. - UnwindOnly declares that this function doesn't handle any exceptions. If it has a handler, it's an unwind handler instead of an exception handler. - Lsda declares the location and size of the LSDA, which in the Win64 EH scheme is kept inside the UNWIND_INFO struct. Windows itself ignores the LSDA; it's used by the Language-Specific Handler (the "Personality Function" from DWARF). llvm-svn: 131572
* Spread use of IRBuilder even more.Devang Patel2011-05-181-10/+12
| | | | llvm-svn: 131571
* Revert r131556; it's breaking buildbots/clang tests.Eli Friedman2011-05-181-247/+0
| | | | llvm-svn: 131567
* Use IRBuilder while simplifying switch instruction.Devang Patel2011-05-181-15/+18
| | | | llvm-svn: 131566
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-1/+1
| | | | | | immediate operand. llvm-svn: 131565
* Use IRBuilder while simplifying unwind.Devang Patel2011-05-181-7/+9
| | | | llvm-svn: 131561
* Enables vararg functions that pass all arguments via registers to be ↵Chad Rosier2011-05-181-5/+18
| | | | | | optimized into tail-calls when possible. llvm-svn: 131560
* More instcombine cleanup aimed towards improving debug line info.Eli Friedman2011-05-181-21/+18
| | | | llvm-svn: 131559
* Second pass at allowing plugins to modify default passes. This time without ↵David Chisnall2011-05-181-0/+247
| | | | | | bonus inter-library dependencies. llvm-svn: 131556
* Revise r131553. Just use the type of the input node and forgo the bitcast. ↵Evan Cheng2011-05-181-4/+3
| | | | | | rdar://9449159. llvm-svn: 131555
* Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same ↵Evan Cheng2011-05-181-1/+3
| | | | | | type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 llvm-svn: 131553
* Use IRBuilder while simplifying terminator.Devang Patel2011-05-181-4/+7
| | | | llvm-svn: 131552
* Use IRBuilder while simplifying unconditional branch.Devang Patel2011-05-181-6/+11
| | | | llvm-svn: 131551
* Use IRBuilder while folding two entry PHINode.Devang Patel2011-05-181-6/+8
| | | | llvm-svn: 131548
* Switch more inst insertion in instcombine to IRBuilder.Eli Friedman2011-05-181-10/+6
| | | | llvm-svn: 131547
* Set up IRBuilder for use during simplification.Devang Patel2011-05-181-0/+3
| | | | llvm-svn: 131545
* Switch more inst insertion in instcombine to IRBuilder.Eli Friedman2011-05-181-13/+6
| | | | llvm-svn: 131544
* fix typoMatt Beaumont-Gay2011-05-181-1/+1
| | | | llvm-svn: 131543
* Switch inst insertion in instcombine transform to IRBuilder.Eli Friedman2011-05-181-6/+2
| | | | llvm-svn: 131542
* Use IRBuiler while constant folding terminator.Devang Patel2011-05-182-9/+12
| | | | llvm-svn: 131541
* Fix inelegant initialization.Stuart Hastings2011-05-181-2/+1
| | | | llvm-svn: 131538
* PTX: add flag to disable mad/fma selectionJustin Holewinski2011-05-184-4/+19
| | | | | | Patch by Dan Bailey llvm-svn: 131537
* Revert commit 131534 since it seems to have broken several buildbots.Duncan Sands2011-05-184-6/+6
| | | | | | | | Original log entry: Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' code in one place. llvm-svn: 131536
* Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem2011-05-184-6/+6
| | | | | | code in one place. llvm-svn: 131534
* Now that SrcBits and DestBits always represent the primitive size, ratherDuncan Sands2011-05-181-55/+29
| | | | | | | | | than either the primitive size or the element primitive size (in the case of vectors), simplify the vector logic. No functionality change. There is some distracting churn in the patch because I lined up comments better while there - sorry about that. llvm-svn: 131533
* Tighten up checking of the validity of casts. (1) The IR parser wouldDuncan Sands2011-05-181-32/+28
| | | | | | | | | | | | | | happily accept things like "sext <2 x i32> to <999 x i64>". It would also accept "sext <2 x i32> to i64", though the verifier would catch that later. Fixed by having castIsValid check that vector lengths match except when doing a bitcast. (2) When creating a cast instruction, check that the cast is valid (this was already done when creating constexpr casts). While there, replace getScalarSizeInBits (used to allow more vector casts) with getPrimitiveSizeInBits in getCastOpcode and isCastable since vector to vector casts are now handled explicitly by passing to the element types; i.e. this bit should result in no functional change. llvm-svn: 131532
* Teach getCastOpcode about element-by-element vector casts. For example, "trunc"Duncan Sands2011-05-181-4/+25
| | | | | | | | | | | | | can be used to turn a <4 x i64> into a <4 x i32> but getCastOpcode would assert if you passed these types to it. Note that this strictly extends the previous functionality: if getCastOpcode previously accepted two vector types (i.e. didn't assert) then it still will and returns the same opcode (BitCast). That's because before it would only accept vectors with the same bitwidth, and the new code only touches vectors with the same length. However if two vectors have both the same bitwidth and the same length then their element types have the same bitwidth, so the new logic will return BitCast as before. llvm-svn: 131530
* In r131488 I misunderstood how VREV works. It splits the vector in half and ↵Tanya Lattner2011-05-182-1343/+1350
| | | | | | | | splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. llvm-svn: 131529
* Implement the Win64 EH directive methods for the assembly language streamer.Charles Davis2011-05-181-0/+77
| | | | | | | | | GAS has no such directives (not even mingw-w64 GAS has them), so I took creative license with their names in assembly. I prefixed them all with "w64_" to avoid namespace collisions, for example. If I discover that GAS has taken a different approach, I'll change ours to match. llvm-svn: 131525
* Eliminate dead dead code elimination code.Jakob Stoklund Olesen2011-05-182-292/+0
| | | | llvm-svn: 131524
* Also use shrinkToUses after AdjustCopiesBackFrom().Jakob Stoklund Olesen2011-05-181-1/+1
| | | | | | | The 'last use' may not be in the same basic block, and we still want a correct live range. llvm-svn: 131523
* While thinking about how to know where the functions' boundaries are forCharles Davis2011-05-181-2/+8
| | | | | | | | | the purposes of the Win64 EH tables, I realized we had no way to tell where the function ends. (MASM bounds functions with PROC and ENDP keywords.) Add a directive to delimit the end of the function, and rename the 'frame' directive to more accurately reflect its duality with the new directive. llvm-svn: 131522
* Properly shrink live ranges after deleting dead copies. Clean up after all ↵Jakob Stoklund Olesen2011-05-181-24/+5
| | | | | | | | | | | | | joined copies. LiveInterval::shrinkToUses recomputes the live range from scratch instead of removing snippets. This should avoid the problem with dangling live ranges. Leave physreg identity copies alone. They can be created when joining a virtreg with a physreg. They don't affect register allocation, and they will be removed by the rewriter. llvm-svn: 131521
* Fix typo.Cameron Zwarich2011-05-181-4/+4
| | | | llvm-svn: 131519
* Fix more of PR8825 by correctly using rGPR registers when lowering atomicCameron Zwarich2011-05-181-2/+11
| | | | | | compare-and-swap intrinsics. llvm-svn: 131518
* Start trying to make InstCombine preserve more debug info. The idea here is ↵Eli Friedman2011-05-182-5/+6
| | | | | | | | | | to set the debug location on the IRBuilder, which will be then right location in most cases. This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder. As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten. Chris, does this approach look reasonable? llvm-svn: 131516
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