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* Updated comments as suggested by Rafael. Thanks.Dinesh Dwivedi2014-06-191-1/+7
| | | | llvm-svn: 211268
* Added instruction combine to transform few more negative values addition to ↵Dinesh Dwivedi2014-06-191-0/+45
| | | | | | | | | | | | subtraction (Part 1) This patch enables transforms for following patterns. (x + (~(y & c) + 1) --> x - (y & c) (x + (~((y >> z) & c) + 1) --> x - ((y>>z) & c) Differential Revision: http://reviews.llvm.org/D3733 llvm-svn: 211266
* [X86] Teach how to combine horizontal binop even in the presence of undefs.Andrea Di Biagio2014-06-191-40/+115
| | | | | | | | | | | | | | Before this change, the backend was unable to fold a build_vector dag node with UNDEF operands into a single horizontal add/sub. This patch teaches how to combine a build_vector with UNDEF operands into a horizontal add/sub when possible. The algorithm conservatively avoids to combine a build_vector with only a single non-UNDEF operand. Added test haddsub-undef.ll to verify that we correctly fold horizontal binop even in the presence of UNDEFs. llvm-svn: 211265
* Refactored and updated SimplifyUsingDistributiveLaws() to Dinesh Dwivedi2014-06-192-105/+142
| | | | | | | | | | | | * Find factorization opportunities using identity values. * Find factorization opportunities by treating shl(X, C) as mul (X, shl(C)) * Keep NSW flag while simplifying instruction using factorization. This fixes PR19263. Differential Revision: http://reviews.llvm.org/D3799 llvm-svn: 211261
* CommandLine: bail out when options get multiply registeredAlp Toker2014-06-191-3/+13
| | | | | | | | | | These errors are strictly unrecoverable and indicate serious issues such as conflicting option names or an incorrectly linked LLVM distribution. With this change, the errors actually get detected so tests don't pass silently. llvm-svn: 211260
* InstCombine: Stop two transforms duelingDavid Majnemer2014-06-191-2/+5
| | | | | | | | | | | | | | | | | | | | | | InstCombineMulDivRem has: // Canonicalize (X+C1)*CI -> X*CI+C1*CI. InstCombineAddSub has: // W*X + Y*Z --> W * (X+Z) iff W == Y These two transforms could fight with each other if C1*CI would not fold away to something simpler than a ConstantExpr mul. The InstCombineMulDivRem transform only acted on ConstantInts until r199602 when it was changed to operate on all Constants in order to let it fire on ConstantVectors. To fix this, make this transform more careful by checking to see if we actually folded away C1*CI. This fixes PR20079. llvm-svn: 211258
* Move -dwarf-version to an MC level command line option so it'sEric Christopher2014-06-192-5/+3
| | | | | | | used by all of the MC level tools and codegen. Fix up all uses in the compiler to use this and set it on the context accordingly. llvm-svn: 211257
* Remove unnecessary include.Eric Christopher2014-06-191-1/+0
| | | | llvm-svn: 211256
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-1914-44/+22
| | | | | | the assert. llvm-svn: 211254
* Move optimization of some cases of (A & C1)|(B & C2) from instcombine to ↵Nick Lewycky2014-06-192-23/+32
| | | | | | instsimplify. Patch by Rahul Jain, plus some last minute changes by me -- you can blame me for any bugs. llvm-svn: 211252
* Make instsimplify's analysis of icmp eq/ne use computeKnownBits to determine ↵Nick Lewycky2014-06-191-0/+19
| | | | | | whether the icmp is always true or false. Patch by Suyog Sarda! llvm-svn: 211251
* Remove redundant code in InstCombineShift, no functionality change because ↵Nick Lewycky2014-06-191-5/+0
| | | | | | instsimplify already does this and instcombine calls instsimplify a few lines above. Patch by Suyog Sarda! llvm-svn: 211250
* MS asm: Properly handle quoted symbol namesDavid Majnemer2014-06-192-3/+17
| | | | | | | | | | | | | We would get confused by '@' characters in symbol names, we would mistake the text following them for the variant kind. When an identifier a string, the variant kind will never show up inside of it. Instead, check to see if there is a variant following the string. This fixes PR19965. llvm-svn: 211249
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-199-13/+127
| | | | | | | | These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. llvm-svn: 211247
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-189-24/+28
| | | | | | | | | This required untangling a mess of headers that included around. This a recommit of r210953 with a fix for the removed accessor for JITInfo. llvm-svn: 211233
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
| | | | llvm-svn: 211231
* Teach llvm-size to know about Mach-O universal files (aka fat files) andKevin Enderby2014-06-181-1/+1
| | | | | | | | | | fat files containing archives. Also fix a bug in MachOUniversalBinary::ObjectForArch::ObjectForArch() where it needed a >= when comparing the Index with the number of objects in a fat file. As the index starts at 0. llvm-svn: 211230
* R600: Handle fnearbyintMatt Arsenault2014-06-182-0/+13
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. llvm-svn: 211229
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-184-26/+175
| | | | | | | | | This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard llvm-svn: 211228
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
| | | | | | This hopefully fixes Windows llvm-svn: 211225
* MC: do not add comment string to the AsmToken in AsmLexer::LexLineCommentSaleem Abdulrasool2014-06-181-2/+2
| | | | | | | | Fixes macros with varargs if the macro instantiation has a trailing comment. Patch by Janne Grunau! llvm-svn: 211219
* MCAsmParser: full support for gas' '.if{cond} expression' directivesSaleem Abdulrasool2014-06-181-8/+41
| | | | | | Patch by Janne Grunau! llvm-svn: 211218
* Replace Execution Engine's mutex with std::recursive_mutex.Zachary Turner2014-06-184-57/+56
| | | | | | | | | | | | | This change has a bit of a trickle down effect due to the fact that there are a number of derived implementations of ExecutionEngine, and that the mutex is not tightly encapsulated so is used by other classes directly. Reviewed by: rnk Differential Revision: http://reviews.llvm.org/D4196 llvm-svn: 211214
* Revert a C API difference that I incorrectly introduced.Rafael Espindola2014-06-182-0/+5
| | | | | | | LLVMGetBitcodeModuleInContext should not take ownership on error. I will try to localize this odd api requirement, but this should get the bots green. llvm-svn: 211213
* Make getBaseObject static.Rafael Espindola2014-06-181-1/+1
| | | | | | Thanks to David Majnemer for noticing. llvm-svn: 211208
* Change IRObjectFile to parse the bitcode lazily.Rafael Espindola2014-06-181-2/+13
| | | | | | | The main point of this class is to provide a cheap object interface to a bitcode file, so it has to be as lazy as possible. llvm-svn: 211207
* Remove BitcodeReader::setBufferOwned.Rafael Espindola2014-06-182-22/+10
| | | | | | | | | | We do have use cases for the bitcode reader owning the buffer or not, but we always know which one we have when we construct it. It might be possible to simplify this further, but this is a step in the right direction. llvm-svn: 211205
* Simply test for available locations in optimization remarks.Diego Novillo2014-06-181-1/+1
| | | | | | | | | | | | | | | | | When emitting optimization remarks, we test for the presence of instruction locations by testing for a valid llvm.dbg.cu annotation. This is slightly inefficient because we can simply ask whether the debug location we have is known or not. Additionally, if my current plan works, I will need to remove the llvm.dbg.cu annotation from the IL (or prevent it from being generated) when -Rpass is used without -g. In those cases, we'll want to generate line tables but we will want to prevent code generation from emitting DWARF code for them. Tested on x86_64. llvm-svn: 211204
* [PowerPC] Remove unnecessary load of r12 in indirect callUlrich Weigand2014-06-181-4/+0
| | | | | | | | | | | | | | | When looking at the 64-bit SVR4 indirect call sequence, I noticed an unnecessary load of r12. And indeed the code says: // R12 must contain the address of an indirect callee. But this is not correct; in the 64-bit SVR4 (ELFv1) ABI, there is no need to load r12 at this point. It seems this code and comment is a remnant of code originally shared with the Darwin ABI ... This patch simply removes the unnecessary load. llvm-svn: 211203
* Run clang-format in a small chunk of code I am about to change.Rafael Espindola2014-06-181-13/+9
| | | | llvm-svn: 211201
* [ARM] [MC] Refactor the constant pool classesWeiming Zhao2014-06-183-136/+97
| | | | | | | | | | | ARMTargetStreamer implements ConstantPool and AssmeblerConstantPools to keep track of assembler-generated constant pools that are used for ldr-pseudo. When implementing ldr-pseudo for AArch64, these two classes can be reused. So this patch factors them out from ARM target to the general MC lib. llvm-svn: 211198
* R600: Expand vector fceilJan Vesely2014-06-181-0/+1
| | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211194
* [PowerPC] Simplify and improve loading into TOC registerUlrich Weigand2014-06-186-40/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During an indirect function call sequence on the 64-bit SVR4 ABI, generate code must load and then restore the TOC register. This does not use a regular LOAD instruction since the TOC register r2 is marked as reserved. Instead, the are two special instruction patterns: let RST = 2, DS = 2 in def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), "ld 2, 8($reg)", IIC_LdStLD, [(PPCload_toc i64:$reg)]>, isPPC64; let RST = 2, DS = 10, RA = 1 in def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), "ld 2, 40(1)", IIC_LdStLD, [(PPCtoc_restore)]>, isPPC64; Note that these not only restrict the destination of the load to r2, but they also restrict the *source* of the load to particular address combinations. The latter is a problem when we want to support the ELFv2 ABI, since there the TOC save slot is no longer at 40(1). This patch replaces those two instructions with a single instruction pattern that only hard-codes r2 as destination, but supports generic addresses as source. This will allow supporting the ELFv2 ABI, and also helps generate more efficient code for calls to absolute addresses (allowing simplification of the ppc64-calls.ll test case). llvm-svn: 211193
* Work around ridiculous warning.Matt Arsenault2014-06-181-2/+5
| | | | | | Apparently C++ doesn't really have hex floating point constants. llvm-svn: 211192
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-186-1/+12
| | | | llvm-svn: 211187
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-182-14/+17
| | | | | | Copy what is done for 32-bit already so the order is about the same. llvm-svn: 211186
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-181-1/+7
| | | | | | but SYNC with an implied operand ($stype = 0) is valid since Mips2. llvm-svn: 211185
* Fix a memory leak in the error path.Rafael Espindola2014-06-181-2/+10
| | | | llvm-svn: 211184
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-182-0/+111
| | | | | | CI has instructions for these, so this fixes them for older hardware. llvm-svn: 211183
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-182-0/+27
| | | | llvm-svn: 211182
* R600/SI: Temporary fix for f64 fnegMatt Arsenault2014-06-181-0/+4
| | | | | | | This should be a source modifier, but this unblocks most of my math patches. llvm-svn: 211181
* R600/SI: Comparisons set vcc.Matt Arsenault2014-06-182-105/+115
| | | | llvm-svn: 211178
* [X86] AVX512: Add non-temporal storesAdam Nemet2014-06-181-0/+29
| | | | | | | | | | | Note that I followed the AVX2 convention here and didn't add LLVM intrinsics for stores. These can be generated with the nontemporal hint on LLVM IR stores (see new test). The GCC builtins are lowered directly into nontemporal stores. <rdar://problem/17082571> llvm-svn: 211176
* [X86] AVX512: Specify compressed displacement for vmovntdqaAdam Nemet2014-06-181-1/+1
| | | | | | | Use the max 64-bit element size with EVEX_CD8. This should work since element size is ignored for a full-vector access (FVM). llvm-svn: 211175
* [PowerPC] Do not use BLA with the 64-bit SVR4 ABIUlrich Weigand2014-06-181-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The PowerPC back-end uses BLA to implement calls to functions at known-constant addresses, which is apparently used for certain system routines on Darwin. However, with the 64-bit SVR4 ABI, this is actually incorrect. An immediate function pointer value on this platform is not directly usable as a target address for BLA: - in the ELFv1 ABI, the function pointer value refers to the *function descriptor*, not the code address - in the ELFv2 ABI, the function pointer value refers to the global entry point, but BL(A) would only be correct when calling the *local* entry point This bug didn't show up since using immediate function pointer values is not usually done in the 64-bit SVR4 ABI in the first place. However, I ran into this issue with a certain use case of LLVM as JIT, where immediate function pointer values were uses to implement callbacks from JITted code to helpers in statically compiled code. Fixed by simply not using BLA with the 64-bit SVR4 ABI. llvm-svn: 211174
* [PowerPC] Fix emitting instruction pairs on LEUlrich Weigand2014-06-181-9/+37
| | | | | | | | | | | | | My patch r204634 to emit instructions in little-endian format failed to handle those special cases where we emit a pair of instructions from a single LLVM MC instructions (like the bl; nop pairs used to implement the call sequence). In those cases, we still need to emit the "first" instruction (the one in the more significant word) first, on both big and little endian, and not swap them. llvm-svn: 211171
* [mips] Fix expansion of memory operation if destination register is not a GPR.Matheus Almeida2014-06-181-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The assembler tries to reuse the destination register for memory operations whenever it can but it's not possible to do so if the destination register is not a GPR. Example: ldc1 $f0, sym should expand to: lui $at, %hi(sym) ldc1 $f0, %lo(sym)($at) It's entirely wrong to expand to: lui $f0, %hi(sym) ldc1 $f0, %lo(sym)($f0) Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4173 llvm-svn: 211169
* [mips] Report correct location when "erroring" about the use of $at when ↵Matheus Almeida2014-06-181-6/+13
| | | | | | | | | | | | | | it's not available. Summary: This removes the FIXMEs from test/MC/Mips/mips-noat.s. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4172 llvm-svn: 211168
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-182-6/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
* [mips] Access $at only if necessary.Matheus Almeida2014-06-181-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch doesn't really change the logic behind expandMemInst but it allows us to assemble .S files that use .set noat with some macros. For example: .set noat lw $k0, offset($k1) Can expand to: lui $k0, %hi(offset) addu $k0, $k0, $k1 lw $k0, %lo(offset)($k0) with no need to access $at. Reviewers: dsanders, vmedic Reviewed By: dsanders, vmedic Differential Revision: http://reviews.llvm.org/D4159 llvm-svn: 211165
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