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* Fix PR5258, jump-threading creating invalid PHIs.Torok Edwin2009-10-201-2/+10
| | | | | | | When an incoming value for a PHI is updated, we must also updated all other incoming values for the same BB to match, otherwise we create invalid PHIs. llvm-svn: 84638
* Fix PR4313: IPSCCP was not setting the lattice value for the invoke instructionTorok Edwin2009-10-201-2/+4
| | | | | | | | | | when the invoke had multiple return values: it set the lattice value only on the extractvalue. This caused the invoke's lattice value to remain the default (undefined), and later propagated to extractvalue's operand, which incorrectly introduces undefined behavior. llvm-svn: 84637
* Random #include pruning.Benjamin Kramer2009-10-201-1/+2
| | | | llvm-svn: 84632
* This file is replaeced by PIC16Section.h.Sanjiv Gupta2009-10-201-88/+0
| | | | llvm-svn: 84628
* implement some more easy hooks.Chris Lattner2009-10-202-3/+34
| | | | llvm-svn: 84614
* Implement some hooks, make printOperand abort if unknown modifiers areChris Lattner2009-10-202-9/+129
| | | | | | present. llvm-svn: 84613
* t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.Chris Lattner2009-10-201-2/+2
| | | | llvm-svn: 84611
* Wire up the ARM MCInst printer, for llvm-mc.Daniel Dunbar2009-10-202-8/+33
| | | | llvm-svn: 84600
* Re-apply r84295, with fixes to how the loop "top" and "bottom" blocks areDan Gohman2009-10-201-182/+343
| | | | | | | | | tracked. Instead of trying to manually keep track of these locations while doing complex modifications, just recompute them when they're needed. This fixes a bug in which the TopMBB and BotMBB were not correctly updated, leading to invalid transformations. llvm-svn: 84598
* Trim unnecessary includes.Evan Cheng2009-10-202-2/+0
| | | | llvm-svn: 84597
* Add getTopBlock and getBottomBlock member functions to MachineLoopInfo.Dan Gohman2009-10-201-0/+28
| | | | llvm-svn: 84596
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-202-15/+0
| | | | | | functions are not needed. llvm-svn: 84587
* If the physical register being spilled does not have an interval, spill its ↵Evan Cheng2009-10-201-5/+21
| | | | | | sub-registers instead. llvm-svn: 84586
* Enable post-pass frame index register scavenging for ARM and Thumb2Jim Grosbach2009-10-203-25/+10
| | | | llvm-svn: 84585
* lower ARM::MOVi32imm properly.Chris Lattner2009-10-201-2/+36
| | | | llvm-svn: 84583
* add support for external symbols. The mc instprinter can now handleChris Lattner2009-10-202-3/+17
| | | | | | | reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing identical output except for superior formatting of constant pool entries. llvm-svn: 84582
* get fancy: support basic block operands. Yay for jumps.Chris Lattner2009-10-203-15/+12
| | | | llvm-svn: 84579
* add supprort for the 'sbit' operand, MOVi apparently has one.Chris Lattner2009-10-203-1/+11
| | | | llvm-svn: 84577
* add support for instruction predicates.Chris Lattner2009-10-202-3/+8
| | | | llvm-svn: 84575
* implement printSORegOperand, add lowering for the nasty and despicable ↵Chris Lattner2009-10-204-5/+75
| | | | | | MOVi2pieces :) llvm-svn: 84573
* Refs: A8-598.Jim Grosbach2009-10-202-10/+24
| | | | | | | | | Leave Inst{11-8}, which represents the starting byte index of the extracted result in the concatenation of the operands and is left unspecified. Patch by Johnny Chen. llvm-svn: 84572
* Add missing encoding bits to NLdSt class of instructions.Jim Grosbach2009-10-201-0/+4
| | | | | | Patch by Johnny Chen. llvm-svn: 84570
* X86 should ignore implicit regs when lowering to MCInst also,Chris Lattner2009-10-191-0/+2
| | | | | | no functionality change. llvm-svn: 84567
* handle addmode4 modifiers, fix a fixme in printRegisterListChris Lattner2009-10-192-10/+4
| | | | | | by ignoring all implicit regs when lowering. llvm-svn: 84566
* simplify by using the twine form of GetOrCreateSymbolChris Lattner2009-10-191-8/+5
| | | | llvm-svn: 84565
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-194-17/+3
| | | | llvm-svn: 84563
* use EmitLabel instead of text emissionChris Lattner2009-10-191-4/+6
| | | | llvm-svn: 84562
* add a twine version of MCContext::GetOrCreateSymbol.Chris Lattner2009-10-193-7/+16
| | | | llvm-svn: 84561
* lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entriesChris Lattner2009-10-193-6/+32
| | | | | | | | | | | | | like: @ BB#1: .align 2 LCPI1_0: .long L_.str-(LPC0+8) Note that proper indentation of the label :) llvm-svn: 84558
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-193-22/+35
| | | | | | | | | | appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. llvm-svn: 84554
* add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.Chris Lattner2009-10-193-5/+34
| | | | llvm-svn: 84553
* Refactor lookup_or_add to contain _MUCH_ less duplicated code. Add support forOwen Anderson2009-10-191-181/+217
| | | | | | numbering first class aggregate instructions while we're at it. llvm-svn: 84547
* add register list and hacked up addrmode #4 support, we now get this:Chris Lattner2009-10-192-2/+48
| | | | | | | | | | | | | | | | | | _main: stmsp! sp!, {r7, lr} mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, [sp] ldr r0, LCPI1_0 bl _printf ldr r0, [sp] mov sp, r7 ldmsp! sp!, {r7, pc} Note the unhappy ldm/stm because of modifiers being ignored. llvm-svn: 84546
* revert r84540, fixing build breakage I didn't see because ofChris Lattner2009-10-192-7/+7
| | | | | | broken makefile deps :( llvm-svn: 84544
* add addrmode2 support, getting us up to:Chris Lattner2009-10-192-1/+35
| | | | | | | | | | | | | | | | _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, [sp] ldr r0, LCPI1_0 bl _printf ldr r0, [sp] mov sp, r7 ldm , llvm-svn: 84543
* add jump tables, constant pools and some trivial globalChris Lattner2009-10-194-22/+94
| | | | | | | | | | | | | | | | | | | | lowering stuff. We can now compile hello world to: _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, ldr r0, bl _printf ldr r0, mov sp, r7 ldm , Almost looks like arm code :) llvm-svn: 84542
* Malloc calls are marked NoAlias, so the code below the isMalloc() check ↵Victor Hernandez2009-10-191-2/+0
| | | | | | makes it redundant. Removing the isMalloc() check. llvm-svn: 84541
* pass mangler in as a reference instead of a pointer.Chris Lattner2009-10-192-7/+7
| | | | llvm-svn: 84540
* reduce #includesChris Lattner2009-10-191-4/+3
| | | | llvm-svn: 84536
* add printing support for SOImm operands, getting us to:Chris Lattner2009-10-193-4/+40
| | | | | | | | | | | _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, llvm-svn: 84535
* Simplify some code.Owen Anderson2009-10-191-124/+61
| | | | llvm-svn: 84533
* wire up some basic printOperand goodness, giving us stuff like this beforeChris Lattner2009-10-193-20/+34
| | | | | | | | | | | | | we abort: _main: stm , mov r7, sp sub sp, sp, mov r0, str r0, llvm-svn: 84532
* add the files that go with the previous revChris Lattner2009-10-192-0/+135
| | | | llvm-svn: 84531
* wire up skeletal support for having llc print instructionsChris Lattner2009-10-192-11/+58
| | | | | | | | through mcinst lowering -> mcinstprinter, when llc is passed the -enable-arm-mcinst-printer flag. Currently this is very "aborty". llvm-svn: 84530
* Banish ConstantsLock. It's serving no purpose other than slowing things downOwen Anderson2009-10-193-60/+22
| | | | | | at the moment. llvm-svn: 84529
* wire up ARM's printMCInst method. Now llvm-mc should be able to produce Chris Lattner2009-10-191-0/+5
| | | | | | | "something" when printing MCInsts, it will just be missing all the operand info. llvm-svn: 84528
* stub out a minimal ARMInstPrinter.Chris Lattner2009-10-193-1/+121
| | | | llvm-svn: 84527
* remove strings from instructions who are never asmprinted.Chris Lattner2009-10-194-30/+15
| | | | | | | | | All of these "subreg32" modifier instructions are handled explicitly by the MCInst lowering phase. If they got to the asmprinter, they would explode. They should eventually be replace with correct use of subregs. llvm-svn: 84526
* Clean up the JITResolver stub/callsite<->function maps.Jeffrey Yasskin2009-10-191-44/+100
| | | | | | | | | | | | | | | | | The JITResolver maps Functions to their canonical stubs and all callsites for lazily-compiled functions to their target Functions. To make Function destruction work, I'm going to need to remove all callsites on destruction, so this patch also adds the reverse mapping for that. There was an incorrect assumption in here that the only stub for a function would be the one caused by needing to lazily compile it, while x86-64 far calls and dlsym-stubs could also cause such stubs, but I didn't look for a test case that the assumption broke. This also adds DenseMapInfo<AssertingVH> so I can use DenseMaps instead of std::maps. llvm-svn: 84522
* simplify code, reducing string thrashing.Chris Lattner2009-10-191-20/+10
| | | | llvm-svn: 84521
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