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* Refactor the DAG Legalizer by extracting the legalization ofNadav Rotem2012-07-111-422/+434
| | | | | | | Load and Store nodes into their own functions. No functional change. llvm-svn: 160037
* Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns ↵Owen Anderson2012-07-111-1/+2
| | | | | | | | an MVT::i1, i.e. before type legalization. This is a speculative fix for a problem on Mips reported by Akira Hatanaka. llvm-svn: 160036
* Lower RETURNADDR node in Mips backend.Akira Hatanaka2012-07-113-5/+31
| | | | | | Patch by Sasa Stankovic. llvm-svn: 160031
* Mips specific inline asm operand modifier 'L'.Jack Carter2012-07-101-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. llvm-svn: 160028
* Require and preserve LoopInfo for early if-conversion.Jakob Stoklund Olesen2012-07-101-0/+17
| | | | | | It will surely be needed by heuristics. llvm-svn: 160027
* Teach the LiveInterval::join function to use the fast merge algorithm,Chandler Carruth2012-07-101-14/+17
| | | | | | | | | | | generalizing its implementation sufficiently to support this value number scenario as well. This cuts out another significant performance hit in large functions (over 10k basic blocks, etc), especially those with "natural" CFG structures. llvm-svn: 160026
* Run early if-conversion in domtree post-order.Jakob Stoklund Olesen2012-07-101-49/+60
| | | | | | | | | | | This ordering allows nested if-conversion without using a work list, and it makes it possible to update the dominator tree on the fly as well. Any erased basic blocks will always be dominated by the current post-order position, so the domtree can be pruned without invalidating the iterator. llvm-svn: 160025
* Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo toChad Rosier2012-07-102-4/+19
| | | | | | | X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. llvm-svn: 160009
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-07-103-14/+106
| | | | | | | | | | | | | X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 llvm-svn: 160002
* Fix a bug where I didn't test for an empty range before inspecting theChandler Carruth2012-07-101-1/+2
| | | | | | | | | | | | | | | back of it. I don't have anything even remotely close to a test case for this. It only broke two build bots, both of them doing bootstrap builds, one of them a dragonegg bootstrap. It doesn't break for me when I bootstrap either. It doesn't reproduce every time or on many machines during the bootstrap. Many thanks to Duncan Sands who got the exact command (and stage of the bootstrap) which failed on the dragonegg bootstrap and managed to get it to trigger under valgrind with debug symbols. The fix was then found by inspection. llvm-svn: 159993
* Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem2012-07-102-28/+55
| | | | | | | | | multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. llvm-svn: 159991
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-102-8/+8
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-101-36/+11
| | | | llvm-svn: 159983
* Add an efficient merge operation to LiveInterval and use it to avoidChandler Carruth2012-07-101-32/+132
| | | | | | | | | | | quadratic behavior when performing pathological merges. Fixes the core element of PR12652. There is only one user of addRangeFrom left: join. I'm hoping to refactor further in a future patch and have join use this merge operation as well. llvm-svn: 159982
* Teach LiveIntervals how to verify themselves and start using it in someChandler Carruth2012-07-101-0/+33
| | | | | | | | | | of the trick merge routines. This adds a layer of testing that was necessary when implementing more efficient (and complex) merge logic for this datastructure. No functionality changed here. llvm-svn: 159981
* ARM: Allow more flexible patterns in NEON formats.Jim Grosbach2012-07-101-53/+53
| | | | | | | | | Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. llvm-svn: 159974
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-109-37/+88
| | | | llvm-svn: 159971
* Delete code for folding undefs in ScalarEvolution. It's invalid inDan Gohman2012-07-091-14/+0
| | | | | | obscure ways, and it isn't actually important in the real world. llvm-svn: 159969
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-092-8/+8
| | | | llvm-svn: 159960
* indentationAndrew Trick2012-07-091-1/+1
| | | | llvm-svn: 159958
* Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional ↵Owen Anderson2012-07-091-0/+36
| | | | | | | | move, since there are only two possible values. Previously, this would become an integer extension operation, followed by a real integer->float conversion. llvm-svn: 159957
* X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren2012-07-091-138/+185
| | | | | | | | | | | getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. llvm-svn: 159955
* Reapply r158846.Akira Hatanaka2012-07-091-114/+77
| | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
* instcombine: merge the functions that remove dead allocas and dead ↵Nuno Lopes2012-07-094-122/+73
| | | | | | | | | mallocs/callocs/... This patch removes ~70 lines in InstCombineLoadStoreAlloca.cpp and makes both functions a bit more aggressive than before :) In theory, we can be more aggressive when removing an alloca than a malloc, because an alloca pointer should never escape, but we are not taking advantage of this anyway llvm-svn: 159952
* Some formatting to keep Clang happyRichard Barton2012-07-091-4/+4
| | | | llvm-svn: 159948
* Oops - correct broken disassembly for VMOVRichard Barton2012-07-091-1/+1
| | | | llvm-svn: 159945
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-092-8/+8
| | | | | | single-precision resiters) llvm-svn: 159938
* Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton2012-07-091-1/+3
| | | | llvm-svn: 159937
* Spelling!Richard Barton2012-07-091-2/+2
| | | | llvm-svn: 159936
* Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton2012-07-091-0/+80
| | | | | | three-register dp instructions where permissable. llvm-svn: 159935
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-0714-59/+104
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Tweak spelling.Andrew Trick2012-07-071-2/+2
| | | | llvm-svn: 159889
* X86: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-071-5/+25
| | | | | | | | It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. llvm-svn: 159888
* Use the DebugInfo wrappers instead of mucking about with the MDNode directly.Bill Wendling2012-07-071-22/+8
| | | | llvm-svn: 159881
* Print the name last.Bill Wendling2012-07-061-5/+4
| | | | llvm-svn: 159879
* Fix the naming of ensureAlignment. Per the coding standard function namesChad Rosier2012-07-061-3/+3
| | | | | | should be camel case, and start with a lower case letter. llvm-svn: 159877
* teach instcombine to remove allocated buffers even if there are stores, ↵Nuno Lopes2012-07-061-2/+25
| | | | | | | | | | | | memcpy/memmove/memset, and objectsize users. This means we can do cheap DSE for heap memory. Nothing is done if the pointer excapes or has a load. The churn in the tests is mostly due to objectsize, since we want to make sure we don't delete the malloc call before evaluating the objectsize (otherwise it becomes -1/0) llvm-svn: 159876
* Check if it's a scope last, because several things are scopes.Bill Wendling2012-07-061-2/+2
| | | | llvm-svn: 159873
* ARM: Add test cleanup entry to the README.Jim Grosbach2012-07-061-0/+21
| | | | llvm-svn: 159864
* revert r159851.Akira Hatanaka2012-07-062-131/+166
| | | | llvm-svn: 159854
* Reapply r158846.Akira Hatanaka2012-07-062-166/+131
| | | | | | Include file MipsGenRegisterInfo.inc. llvm-svn: 159851
* Add a print method to the ObjC property object.Bill Wendling2012-07-061-0/+11
| | | | llvm-svn: 159848
* Remove trailing comma in array initialization list.Bill Wendling2012-07-061-8/+8
| | | | llvm-svn: 159843
* Remove unnecessary 'llvm::'.Bill Wendling2012-07-061-19/+19
| | | | llvm-svn: 159842
* Remove unnecessary 'llvm::'.Bill Wendling2012-07-061-4/+4
| | | | llvm-svn: 159841
* Whitespace.Chad Rosier2012-07-061-3/+3
| | | | llvm-svn: 159839
* X86: peephole optimization to remove cmp instructionManman Ren2012-07-063-0/+302
| | | | | | | | For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. llvm-svn: 159838
* [fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.Chad Rosier2012-07-061-0/+3
| | | | llvm-svn: 159837
* Revert r159804, "[arm-fast-isel] Add support for vararg function calls."NAKAMURA Takumi2012-07-061-33/+26
| | | | | | It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts. llvm-svn: 159817
* Fix PR13202 and a regtest.Alexey Samsonov2012-07-061-0/+6
| | | | | | | | | | | | | DwarfDebug class could generate the same (inlined) DIVariable twice: 1) when trying to find abstract debug variable for a concrete inlined instance. 2) when explicitly collecting info for variables that were optimized out. This change makes sure that this duplication won't happen and makes Clang pass "gdb.opt/inline-locals" test from gdb testsuite. Reviewed by Eric Christopher. llvm-svn: 159811
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