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* [RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury2018-05-172-0/+6
| | | | | | | | | | These directives are recognised by gas. Support is added through the use of addAliasForDirective. Also match RISC-V gcc in preferring .half and .word for 16-bit and 32-bit data directives. llvm-svn: 332574
* [X86] Add OptForSize to a couple load folding patterns. Remove some bad ↵Craig Topper2018-05-172-10/+7
| | | | | | | | FIXME comments. The FIXME comments were about preventing load folding to avoid a partial xmm update. But these instructions use GPR as input when the load isn't folded. This won't help prevent a partial xmm update. llvm-svn: 332573
* [WebAssembly] Fix the opcode number for i64.load16_u.Dan Gohman2018-05-171-1/+1
| | | | | | Fixes PR37488. llvm-svn: 332561
* [CodeGen] Use MachineInstr::getOperand(0) instead of gets the defs ↵Craig Topper2018-05-161-1/+1
| | | | | | | | iterator_range and calling begin. NFC Defs are well defined to come first in MachineInstr operand list. No need for a more complex indirection. llvm-svn: 332559
* Revert 332508 as it caused problems in the clang test suite.Greg Clayton2018-05-161-4/+0
| | | | llvm-svn: 332555
* [STLExtras] Add size() for ranges, and remove distance()Vedant Kumar2018-05-165-7/+10
| | | | | | | | | | r332057 introduced distance() for ranges. Based on post-commit feedback, this renames distance() to size(). The new size() is also only enabled when the operation is O(1). Differential Revision: https://reviews.llvm.org/D46976 llvm-svn: 332551
* [NFC] WebAssembly build break #2JF Bastien2018-05-161-0/+4
| | | | | | | | | | | | | | | | | Summary: Same as r332530, move WasmSymbol::dump to an implementation file to avoid linker issues when the dump function is seen in the header, doesn't get eliminated, and then linking fails because of the missing dependency. <rdar://problem/40258137> Reviewers: sbc100, ncw, paquette, vsk, dschuff Subscribers: jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D46985 llvm-svn: 332542
* [ORC] Rewrite the VSO symbol table yet again. Update related utilities.Lang Hames2018-05-164-438/+694
| | | | | | | | | | | | | | | | | | | VSOs now track dependencies for materializing symbols. Each symbol must have its dependencies registered with the VSO prior to finalization. Usually this will involve registering the dependencies returned in AsynchronousSymbolQuery::ResolutionResults for queries made while linking the symbols being materialized. Queries against symbols are notified that a symbol is ready once it and all of its transitive dependencies are finalized, allowing compilation work to be broken up and moved between threads without queries returning until their symbols fully safe to access / execute. Related utilities (VSO, MaterializationUnit, MaterializationResponsibility) are updated to support dependence tracking and more explicitly track responsibility for symbols from the point of definition until they are finalized. llvm-svn: 332541
* [X86][SNB] Remove unnecessary CVT InstRW overridesSimon Pilgrim2018-05-161-82/+24
| | | | llvm-svn: 332536
* [WebAssembly] Remove unused headers in MCWasmObjectWriterSam Clegg2018-05-161-3/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D46969 llvm-svn: 332535
* [InstCombine] Fix the signature of fgets_unlocked.Benjamin Kramer2018-05-161-2/+2
| | | | | | | It returns a pointer, not an int. This miscompiles all code that uses the return value of fgets. llvm-svn: 332531
* [NFC] WebAssembly build fixJF Bastien2018-05-161-0/+13
| | | | | | | | | | | | | | | | | | | | | | Summary: r332305 added a use of llvm::wasm::toString in llvm::object::WasmSymbol::print, which is in a header file. It also moves toString to BinaryFormat. This has the unintended side-effect that any inclusion of Object/Wasm.h now relies on toString, and needs to required_libraries = BinaryFormat. Thankfully most builds don't fail with this because print just isn't used and gets eliminated, dropping the required dependency in the process. Not all builds are so lucky. Fix this issue by moving print to the corresponding .cpp file. <rdar://problem/40258137> Reviewers: sbc100, ncw, paquette Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D46977 llvm-svn: 332530
* [MachineOutliner] Don't outline instructions that modify SP.Eli Friedman2018-05-161-0/+8
| | | | | | | | | | | | | This breaks the code which saves and restores LR, so we can't outline without doing something more complicated for stack adjustment. Found by inspection; we get lucky in most cases because getMemOpInfo only handles STRWpost, not any other pre/post-increment forms. But it hits a couple of artificial testcases in the tree. Differential Revision: https://reviews.llvm.org/D46920 llvm-svn: 332529
* [Hexagon] Fix the order of operands when selecting QCATKrzysztof Parzyszek2018-05-161-2/+2
| | | | llvm-svn: 332526
* [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patternsKrzysztof Parzyszek2018-05-162-35/+73
| | | | llvm-svn: 332525
* [X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)Simon Pilgrim2018-05-161-16/+39
| | | | | | | | | | As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
* AMDGPU : Recalculate SGPRs when trap handler is supportedKonstantin Zhuravlyov2018-05-162-6/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D29911 llvm-svn: 332523
* Fix small grammar-o.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332522
* Fix up a misleading format warning.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332521
* [WebAssembly] MC: Ensure that FUNCTION_OFFSET relocations are always against ↵Sam Clegg2018-05-161-1/+17
| | | | | | | | | | | | | | | | | function symbols. The getAtom() method wasn't doing what we needed in all cases. We want the symbols for the function which defines that section. We can compute this easily enough and we know that we have at most one function in each section. Once this lands I will revert rL331412 which is no longer needed. Fixes PR37409 Differential Revision: https://reviews.llvm.org/D46970 llvm-svn: 332517
* [MachineOutliner] Don't save/restore LR for tail calls.Eli Friedman2018-05-161-3/+4
| | | | | | | | | The cost computation assumes we do this correctly, but the actual lowering was wrong. Differential Revision: https://reviews.llvm.org/D46923 llvm-svn: 332514
* [X86] Fix typo in instregex for CVTSI642SDrrSimon Pilgrim2018-05-161-1/+1
| | | | llvm-svn: 332510
* Fix llvm::sys::path::remove_dots() to return "." instead of an empty path.Greg Clayton2018-05-161-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D46887 llvm-svn: 332508
* [Timers] TimerGroup: add constructor from StringMap<TimeRecord>Roman Lebedev2018-05-161-0/+9
| | | | | | | | | | | | | | | | Summary: This is needed for the continuation of D46504, to be able to store the timings. Reviewers: george.karpenkov, NoQ, alexfh, sbenza Reviewed By: alexfh Subscribers: llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D46939 llvm-svn: 332506
* [Timers] TimerGroup: make printJSONValues() method publicRoman Lebedev2018-05-161-0/+2
| | | | | | | | | | | | | | | | Summary: This is needed for the continuation of D46504, to be able to store the timings. Reviewers: george.karpenkov, NoQ, alexfh, sbenza Reviewed By: alexfh Subscribers: llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D46938 llvm-svn: 332505
* [Timers] TimerGroup::printJSONValue(): print doubles with no precision lossRoman Lebedev2018-05-161-3/+7
| | | | | | | | | | | | | | | | Summary: Although this is not stricly required, i would very much prefer not to have known random precision losses along the way. Reviewers: george.karpenkov, NoQ, alexfh, sbenza Reviewed By: george.karpenkov Subscribers: llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D46937 llvm-svn: 332504
* [Timers] TimerGroup::printJSONValues(): print mem timer with .mem suffixRoman Lebedev2018-05-161-1/+1
| | | | | | | | | | | | | | Summary: We have just used `.sys` suffix for the previous timer, this is clearly a typo Reviewers: george.karpenkov, NoQ, alexfh, sbenza Reviewed By: alexfh Subscribers: llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D46936 llvm-svn: 332503
* [X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on ↵Craig Topper2018-05-161-8/+62
| | | | | | | | | | | | 32-bit targets As i64 types are not legal on 32-bit targets, insert these into a suitable zero vector and use the packed vXi64<->FP conversion instructions instead. Fixes PR3163. Differential Revision: https://reviews.llvm.org/D43441 llvm-svn: 332498
* Signal handling should be signal-safeJF Bastien2018-05-163-84/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this patch, signal handling wasn't signal safe. This leads to real-world crashes. It used ManagedStatic inside of signals, this can allocate and can lead to unexpected state when a signal occurs during llvm_shutdown (because llvm_shutdown destroys the ManagedStatic). It also used cl::opt without custom backing storage. Some de-allocation was performed as well. Acquiring a lock in a signal handler is also a great way to deadlock. We can't just disable signals on llvm_shutdown because the signals might do useful work during that shutdown. We also can't just disable llvm_shutdown for programs (instead of library uses of clang) because we'd have to then mark the pointers as not leaked and make sure all the ManagedStatic uses are OK to leak and remain so. Move all of the code to lock-free datastructures instead, and avoid having any of them in an inconsistent state. I'm not trying to be fancy, I'm not using any explicit memory order because this code isn't hot. The only purpose of the atomics is to guarantee that a signal firing on the same or a different thread doesn't see an inconsistent state and crash. In some cases we might miss some state (for example, we might fail to delete a temporary file), but that's fine. Note that I haven't touched any of the backtrace support despite it not technically being totally signal-safe. When that code is called we know something bad is up and we don't expect to continue execution, so calling something that e.g. sets errno is the least of our problems. A similar patch should be applied to lib/Support/Windows/Signals.inc, but that can be done separately. Fix r332428 which I reverted in r332429. I originally used double-wide CAS because I was lazy, but some platforms use a runtime function for that which thankfully failed to link (it would have been bad for signal handlers otherwise). I use a separate flag to guard the data instead. <rdar://problem/28010281> Reviewers: dexonsmith Subscribers: steven_wu, llvm-commits llvm-svn: 332496
* [DAG] Prune cycle check in store merge.Nirav Dave2018-05-161-18/+54
| | | | | | | | | | | | | | | | | | | | As part of merging stores we check that fusing the nodes does not cause a cycle due to one candidate store being indirectly dependent on another store (this may happen via chained memory copies). This is done by searching if a store is a predecessor to another store's value. Prune the search at the candidate search's root node which is a predecessor to all candidate stores. This reduces the size of the subgraph searched in large basic blocks. Reviewers: jyknight Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D46955 llvm-svn: 332490
* [DAG] Defer merge store cycle checking to just before merge. NFCI.Nirav Dave2018-05-161-8/+20
| | | | llvm-svn: 332489
* [AMDGPU] Change llvm.debugtrap to be a debug breakpoint that can resume ↵Tony Tye2018-05-162-34/+34
| | | | | | | | | | execution. No longer require the queue pointer to be passed in in fixed SGPRs. Differential Revision: https://reviews.llvm.org/D46769 llvm-svn: 332485
* [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.Sander de Smalen2018-05-162-11/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For regular SVE vector operands, this patch introduces a more sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b). For example: add z0.s, z1.s, z2.b -> invalid element width ^_____^ mismatch For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes a slightly different approach and instead returns a 'invalid operand' if the element size is not as expected. This is because the diagnostics are more specificied to suggest using the right shift/extend suffix. This is a trade-off not to introduce more operand classes and still provide useful diagnostics for LD1 and PRF instructions. For example: ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand ^________________^ mismatch For gather prefetches, both 'z0.s' and 'z0.d' would be allowed: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' Without this change, the diagnostic would unnecessarily suggest a different element size: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46688 llvm-svn: 332483
* [AArch64] Gangup loads and stores for pairing.Sirish Pande2018-05-163-4/+88
| | | | | | | | | | Keep loads and stores together (target defines how many loads and stores to gang up), such that it will help in pairing and vectorization. Differential Revision https://reviews.llvm.org/D46477 llvm-svn: 332482
* [InstCombine] allow more binop (shuffle X), C transformsSanjay Patel2018-05-161-2/+4
| | | | | | | | | The canonicalization was restricted to shuffle masks with a 1-to-1 mapping to the constant vector, but that disqualifies the common splat pattern. This is part of solving PR37463: https://bugs.llvm.org/show_bug.cgi?id=37463 llvm-svn: 332479
* [AArch64][SVE] Asm: Support for gather PRF prefetch instructionsSander de Smalen2018-05-162-0/+159
| | | | | | | | | | Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46686 llvm-svn: 332472
* [BasicAA] Fix handling of invariant group laundersKrzysztof Pszeniczny2018-05-162-1/+14
| | | | | | | | | | | | | | | | | Summary: A recent patch ([[ https://reviews.llvm.org/rL331587 | rL331587 ]]) to Capture Tracking taught it that the `launder_invariant_group` intrinsic captures its argument only by returning it. Unfortunately, BasicAA still considered every call instruction as a possible escape source and hence concluded that the result of a `launder_invariant_group` call cannot alias any local non-escaping value. This led to [[ https://bugs.llvm.org/show_bug.cgi?id=37458 | bug 37458 ]]. This patch updates the relevant check for escape sources in BasicAA. Reviewers: Prazek, kuhar, rsmith, hfinkel, sanjoy, xbolva00 Reviewed By: hfinkel, xbolva00 Subscribers: JDevlieghere, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46900 llvm-svn: 332466
* [mips] Simplify some of the predicate scopes for (negative) multiply add/sub ↵Simon Dardis2018-05-161-23/+20
| | | | | | instructions (NFCI) llvm-svn: 332464
* [mips] Join existing scopes for DecoderNamespace (NFCI)Simon Dardis2018-05-161-6/+3
| | | | llvm-svn: 332462
* AMDGPU: Custom lower v4i16/v4f16 vector operationsMatt Arsenault2018-05-164-19/+124
| | | | | | | | | Avoids stack access. Also handle extract hi elt pattern from truncate + shift to avoid a couple test regressions. llvm-svn: 332453
* [SimplifyLibcalls] Replace locked IO with unlocked IODavid Bolvansky2018-05-163-20/+258
| | | | | | | | | | | | | | Summary: If file stream arg is not captured and source is fopen, we could replace IO calls by unlocked IO ("_unlocked" function variants) to gain better speed, Reviewers: efriedma, RKSimon, spatel, sanjoy, hfinkel, majnemer, lebedev.ri, rja Reviewed By: rja Subscribers: rja, srhines, efriedma, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D45736 llvm-svn: 332452
* [X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classesSimon Pilgrim2018-05-1614-359/+338
| | | | | | A lot of the models still have too many InstRW overrides for these new classes - this needs cleaning up but I wanted to get the classes in first llvm-svn: 332451
* [LoopUnroll] Split out simplify code after Unroll into a new function. NFCDavid Green2018-05-161-34/+46
| | | | | | | | | So that it can be shared with other passes that may end up doing the same thing. Differential Revision: https://reviews.llvm.org/D45874 llvm-svn: 332450
* [GlobalISel][IRTranslator] Split aggregates during IR translation.Amara Emerson2018-05-163-136/+289
| | | | | | | | | | | | | | | | | | | | | We currently handle all aggregates by creating one large LLT, and letting the legalizer deal with splitting them up. However using this approach means that we can't support big endian code correctly. This patch changes the way that the IRTranslator deals with aggregate values, by splitting them up into their constituent element values. To do this, parts of the translator need to be modified to deal with multiple VRegs for a single Value. A new Value to VReg mapper is introduced to help keep compile time under control, currently there is no measurable impact on CTMark despite the extra code being generated in some cases. Patch is based on the original work of Tim Northover. Differential Revision: https://reviews.llvm.org/D46018 llvm-svn: 332449
* [mips] Add support for isBranchOffsetInRange and use it for MipsLongBranchSimon Dardis2018-05-164-14/+205
| | | | | | | | | | | | Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
* [AArch64] Support "S" inline assembler constraintPeter Smith2018-05-162-1/+25
| | | | | | | | | | | | | | | | | | | | | This patch re-introduces the "S" inline assembler constraint. This matches an absolute symbolic address or a label reference. The primary use case is asm("adrp %0, %1\n\t" "add %0, %0, :lo12:%1" : "=r"(addr) : "S"(&var)); I say re-introduces as it seems like "S" was implemented in the original AArch64 backend, but it looks like it wasn't carried forward to the merged backend. The original implementation had A and L modifiers that could be used to print ":lo12:" to the string. It looks like gcc doesn't use these and :lo12: is expected to be written in the inline assembly string so I've not implemented A and L. Clang already supports the S modifier. Fixes PR37180 Differential Revision: https://reviews.llvm.org/D46745 llvm-svn: 332444
* [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) ↵Sander de Smalen2018-05-162-0/+36
| | | | | | | | | | | | load instructions. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46679 llvm-svn: 332442
* Emit a left-shift instead of a power-of-two multiply for jump-tablesAlexander Richardson2018-05-161-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a BR_JT opcode. While many backends optimize this multiply into a shift, e.g. the MIPS backend currently always lowers this into a sequence of load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv(). I initially changed the multiply to a shift in the MIPS backend but it turns out that would not have handled the MIPSR6 case and was a lot more code than doing it in LegalizeDAG. I believe performing this simple optimization in LegalizeDAG instead of each individual backend is the better solution since this also fixes other backeds such as MSP430 which calls the multiply runtime function __mspabi_mpyi without this patch. Reviewers: sdardis, atanasyan, pftbest, asl Reviewed By: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45760 llvm-svn: 332439
* [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions.Sander de Smalen2018-05-164-2/+77
| | | | | | | | | | Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46682 llvm-svn: 332433
* [Unix] Indent ChangeStd{in,out}ToBinary.Fangrui Song2018-05-161-4/+4
| | | | llvm-svn: 332432
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