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| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-16 12:44:27 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-16 12:44:27 +0000 |
| commit | 8ea0ecdedcdc226b5f50f3a8ed40ca2255f877ec (patch) | |
| tree | 96ee7b0531933df8f3150419e7ea365289509bbd /llvm/lib | |
| parent | afe62cdc4e411953f3ceea398ad50d9862323dd7 (diff) | |
| download | bcm5719-llvm-8ea0ecdedcdc226b5f50f3a8ed40ca2255f877ec.tar.gz bcm5719-llvm-8ea0ecdedcdc226b5f50f3a8ed40ca2255f877ec.zip | |
[mips] Simplify some of the predicate scopes for (negative) multiply add/sub instructions (NFCI)
llvm-svn: 332464
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 43 |
1 files changed, 20 insertions, 23 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 96e5457952a..e943e322218 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -608,41 +608,38 @@ let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; -} -let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { - def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, - MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; - def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, - MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; -} -let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; + + let DecoderNamespace = "MipsFP64" in { + def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, + MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; + def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, + MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; + } } + let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { + def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, + MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; + def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, + MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; + def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; -} -let AdditionalPredicates = [NotInMicroMips, HasMadd4, NotInMicroMips], - DecoderNamespace = "MipsFP64" in { - def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, - MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; - def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; -} -let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips], - DecoderNamespace = "MipsFP64" in { - def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, - MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; - def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, - MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; -} + let DecoderNamespace = "MipsFP64" in { + def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, + MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; + def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, + MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; + } +} //===----------------------------------------------------------------------===// // Floating Point Branch Codes //===----------------------------------------------------------------------===// |
