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* [mips] Initial implementation of -mabicalls/-mno-abicalls.Daniel Sanders2014-08-085-9/+20
| | | | | | | | | | | This patch implements the main rules for -mno-abicalls such as reserving $gp, and emitting the correct .option directive. Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4231 llvm-svn: 215194
* AArch64: stop trying to take control of all UnknownArch triples.Tim Northover2014-08-081-2/+3
| | | | | | | | | This short-circuited our error reporting for incorrectly specified target triples (you'd get AArch64 code instead). Should fix PR20567. llvm-svn: 215191
* [pr19635] Revert most of r170537, and add new testcase.Patrik Hagglund2014-08-083-5/+5
| | | | | | | | Patch provided by Andrey Kuharev. Sorry, r170537 was obviously wrong. llvm-svn: 215190
* GlobalOpt: Optimize in the face of insertvalue/extractvalueDavid Majnemer2014-08-081-0/+11
| | | | | | | | | | GlobalOpt didn't know how to simulate InsertValueInst or ExtractValueInst. Optimizing these is pretty straightforward. N.B. This came up when looking at clang's IRGen for MS ABI member pointers; they are represented as aggregates. llvm-svn: 215184
* AArch64InstrInfo.cpp: Fix \param(s). [-Wdocumentation]NAKAMURA Takumi2014-08-081-2/+2
| | | | llvm-svn: 215180
* [tablegen] - Eliminate memory leaks in TGParser.cppAnton Yartsev2014-08-081-4/+26
| | | | | | Ugly solution indicating that a refactoring is necessary to get the ownership under control. llvm-svn: 215176
* [AVX512] Add zero-masking variant to AVX512_masking multiclassAdam Nemet2014-08-071-2/+12
| | | | | | | | | | | This completes one item from the todo-list of r215125 "Generate masking instruction variants with tablegen". The AddedComplexity is needed just like for the k variant. Added a codegen test based on valignq. llvm-svn: 215173
* Fix for multi-line comment warningGerolf Hoflehner2014-08-071-12/+12
| | | | llvm-svn: 215169
* [AVX512] Add codegen test for the masking variant of valignAdam Nemet2014-08-071-2/+3
| | | | | | | The AddedComplexity is needed just like in avx512_perm_3src. There may be a bug in the complexity computation... llvm-svn: 215168
* [stack protector] Look through bitcasts to get global variableAkira Hatanaka2014-08-071-9/+19
| | | | | | | | | | | | | | | | __stack_chk_guard. Handle the case where the pointer operand of the load instruction that loads the stack guard is not a global variable but instead a bitcast. %StackGuard = load i8** bitcast (i64** @__stack_chk_guard to i8**) call void @llvm.stackprotector(i8* %StackGuard, i8** %StackGuardSlot) Original test case provided by Ana Pazos. This fixes PR20558. llvm-svn: 215167
* SLPVectorizer: Use the type of the value loaded/stored to get the ABI alignmentArnold Schwaighofer2014-08-071-2/+3
| | | | | | We were using the pointer type which is incorrect. llvm-svn: 215162
* DebugInfo: Fix overwriting/loss of inlined arguments to recursively inlined ↵David Blaikie2014-08-071-4/+2
| | | | | | | | | | | | | | | | | | | | | functions. Due to an unnecessary special case, inlined arguments that happened to be from the same function as they were inlined into were misclassified as non-inline arguments and would overwrite the non-inlined arguments. Assert that we never overwrite a function's arguments, and stop misclassifying inlined arguments as non-inline arguments to fix this issue. Excuse the rather crappy test case - handcrafted IR might do better, or someone who understands better how to tickle the inliner to create a recursive inlining situation like this (though it may also be necessary to tickle the variable in a particular way to cause it to be recorded in the MMI side table and go down this particular path for location information). llvm-svn: 215157
* fix materialization of one bit constants and global values which are ↵Reed Kotler2014-08-071-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | accessed through a base GOT entry. Summary: get tip of tree mips fast-isel to pass test-suite Two bugs were fixed: 1) one bit booleans were treated as 1 bit signed integers and so the literal '1' could become sign extended. 2) mips uses got for pic but in certain cases, as with string constants for example, many items can be referenced from the same got entry and this case was not handled properly. Test Plan: test-suite Reviewers: dsanders Reviewed By: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D4801 llvm-svn: 215155
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-0788-61/+9474
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Debugging Utility - optional ability for dumping critical path lengthGerolf Hoflehner2014-08-071-2/+16
| | | | llvm-svn: 215153
* MachineCombiner Pass for selecting faster instruction sequence on AArch64Gerolf Hoflehner2014-08-076-14/+539
| | | | | | | | | | Re-commit of r214832,r21469 with a work-around that avoids the previous problem with gcc build compilers The work-around is to use SmallVector instead of ArrayRef of basic blocks in preservesResourceLen()/MachineCombiner.cpp llvm-svn: 215151
* Add two missing ARM cpusubtypes to the switch statement in Kevin Enderby2014-08-071-0/+4
| | | | | | | | | MachOObjectFile::getArch(uint32_t CPUType, uint32_t CPUSubType) . Upcoming changes will cause existing test cases to use this but I wanted to check in this obvious change separately. llvm-svn: 215150
* Fix a case in SROA where lifetime intrinsics could inhibit alloca promotion. InOwen Anderson2014-08-071-0/+4
| | | | | | | | this case, the code path dealing with vector promotion was missing the explicit checks for lifetime intrinsics that were present on the corresponding integer promotion path. llvm-svn: 215148
* [MCJIT] Replace a c-style cast with reinterpret_cast + static_cast.Lang Hames2014-08-071-4/+4
| | | | | | | | | | C-style casts (and reinterpret_casts) result in implementation defined values when a pointer is cast to a larger integer type. On some platforms this was leading to bogus address computations in RuntimeDyldMachOAArch64. This should fix http://llvm.org/PR20501. llvm-svn: 215143
* Remove Support/IncludeFile.h and its only user. This is actively harmful, sinceRichard Smith2014-08-073-24/+0
| | | | | | | | | | | | | it breaks the modules builds (where CallGraph.h can be quite reasonably transitively included by an unimported portion of a module, and CallGraph.cpp not linked in), and appears to have been entirely redundant since PR780 was fixed back in 2008. If this breaks anything, please revert; I have only tested this with a single configuration, and it's possible that this is still somehow fixing something (though I doubt it, since no other similar file uses this mechanism any more). llvm-svn: 215142
* test commit: remove trailing whitespace.Frederic Riss2014-08-071-2/+2
| | | | llvm-svn: 215138
* [Branch probability] Recompute branch weights of tail-merged basic blocks.Akira Hatanaka2014-08-073-8/+101
| | | | | | | | | | | | | | | BranchFolderPass was not correctly setting the basic block branch weights when tail-merging created or merged blocks. This patch recomutes the weights of tail-merged blocks using the following formula: branch_weight(merged block to successor j) = sum(block_frequency(bb) * branch_probability(bb -> j)) bb is a block that is in the set of merged blocks. <rdar://problem/16256423> llvm-svn: 215135
* Add the majority of the remaining SPE instructions.Joerg Sonnenberger2014-08-071-0/+319
| | | | llvm-svn: 215131
* [AVX512] Generate masking instruction variants with tablegenAdam Nemet2014-08-072-20/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After adding the masking variants to several instructions, I have decided to experiment with generating these from the non-masking/unconditional variant. This will hopefully reduce the amount repetition that we currently have in order to define an instruction with all its variants (for a reg/mem instruction this would be 6 instruction defs and 2 Pat<> for the intrinsic). The patch is the first cut that is currently only applied to valignd/q to make the patch small. A few notes on the approach: * In order to stitch together the dag for both the conditional and the unconditional patterns I pass the RHS of the set rather than the full pattern (set dest, RHS). * Rather than subclassing each instruction base class (e.g. AVX512AIi8), with a masking variant which wouldn't scale, I derived the masking instructions from a new base class AVX512 (this is just I<> with Requires<HasAVX512>). The instructions derive from this now, plus a new set of classes that add the format bits and everything else that instruction base class provided (i.e. AVX512AIi8 vs. AVX512AIi8Base). I hope we can go incrementally from here. I expect that: * We will need different variants of the masking class. One example is instructions requiring three vector sources. In this case we tie one of the source operands to dest rather than a new implicit source operand ($src0) * Add the zero-masking variant * Add more AVX512*Base classes as new uses are added I've looked at X86.td.expanded before and after to make sure that nothing got lost for valignd/q. llvm-svn: 215125
* fix configure+make buildRafael Espindola2014-08-072-2/+1
| | | | llvm-svn: 215116
* Nuke the old JIT.Rafael Espindola2014-08-0786-9472/+60
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Add mfasr and mtasrJoerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215110
* Add mfrtcu and mfrtcl instructionsJoerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215109
* Support mttbl and mttbu mnemonicJoerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215108
* Add RFID instruction.Joerg Sonnenberger2014-08-071-0/+2
| | | | llvm-svn: 215105
* Fix Itineray class of rfiJoerg Sonnenberger2014-08-071-1/+1
| | | | llvm-svn: 215104
* Spell e500 feature in lower case.Joerg Sonnenberger2014-08-071-1/+1
| | | | llvm-svn: 215103
* Add first bunch of SPE instructions. As they overlap with Altivec, markJoerg Sonnenberger2014-08-075-1/+78
| | | | | | | them as parser-only until the disassembler is extended to handle predicates properly. llvm-svn: 215102
* Insert parens to avoid a warning:Alexander Kornienko2014-08-071-1/+1
| | | | | | suggest parentheses around arithmetic in operand of '^' [-Wparentheses] llvm-svn: 215101
* Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly ↵Aaron Ballman2014-08-071-1/+1
| | | | | | converted to 64 bits (was 64-bit shift intended?)). No functional changes intended. llvm-svn: 215100
* [mips] Add assembler support for .set msa/nomsa directive.Daniel Sanders2014-08-073-0/+46
| | | | | | | | | | | | | | | Summary: These directives are used to toggle whether the assembler accepts MSA-specific instructions or not. Patch by Matheus Almeida and Toma Tabacu. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4783 llvm-svn: 215099
* Fix lld-x86_64-win7 Build #11969Pavel Chupin2014-08-071-2/+2
| | | | llvm-svn: 215097
* [x86] Fix another miscompile found through fuzz testing the new vectorChandler Carruth2014-08-071-4/+4
| | | | | | | | | | | | | | shuffle lowering. This is closely related to the previous one. Here we failed to use the source offset when swapping in the other case -- where we end up swapping the *final* shuffle. The cause of this bug is a bit different: I simply wasn't thinking about the fact that this mask is actually a slice of a wide mask and thus has numbers that need SourceOffset applied. Simple fix. Would be even more simple with an algorithm-y thing to use here, but correctness first. =] llvm-svn: 215095
* [x86] Fix another miscompile in the new vector shuffle lowering foundChandler Carruth2014-08-071-1/+1
| | | | | | | | | | | | via the fuzz tester. Here I missed an offset when round-tripping a value through a shuffle mask. I got it right 2 lines below. See a problem? I do. ;] I'll probably be adding a little "swap" algorithm which accepts a range and two values and swaps those values where they occur in the range. Don't really have a name for it, let me know if you do. llvm-svn: 215094
* [x86] Fix another miscompile in the new vector shuffle lowering foundChandler Carruth2014-08-071-1/+1
| | | | | | | | | | | | through the new fuzzer. This one is great: bad operator precedence led the modulus to happen at the wrong point. All the asserts didn't fire because there were usually the right values past the end of the 4 element region we were looking at. Probably could have gotten a crash here with ASan + fuzzing, but the correctness tests pinpointed this really nicely. llvm-svn: 215092
* [x32] Use ebp/esp as frame and stack pointerPavel Chupin2014-08-074-40/+45
| | | | | | | | | | | | | | | | | | | | | | | Summary: Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still require 64-bit register, so using 64-bit MachineFramePtr where required. X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing this issue here as well by making isTarget64BitLP64 false. Also mark hasReservedSpillSlot unreachable on X86. See inlined comments. Test Plan: Add one new simple test and upgrade 2 existing with x32 target case. Reviewers: nadav, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4617 llvm-svn: 215091
* [x86] Fix a miscompile in the new shuffle lowering found through the newChandler Carruth2014-08-071-6/+6
| | | | | | | | | | | | | | | | | | | | fuzz testing. The function which tested for adjacency did what it said on the tin, but when I called it, I wanted it to do something more thorough: I wanted to know if the *pairs* of shuffle elements were adjacent and started at 0 mod 2. In one place I had the decency to try to test for this, but in the other it was completely skipped, miscompiling this test case. Fix this by making the helper actually do what I wanted it to do everywhere I called it (and removing the now redundant code in one place). I *really* dislike the name "canWidenShuffleElements" for this predicate. If anyone can come up with a better name, please let me know. The other name I thought about was "canWidenShuffleMask" but is it really widening the mask to reduce the number of lanes shuffled? I don't know. Naming things is hard. llvm-svn: 215089
* Update BitRecTy::convertValue to allow if expressions with bit values on ↵Pete Cooper2014-08-071-0/+10
| | | | | | both sides of the if llvm-svn: 215087
* Change the { } expression in tablegen to accept sized binary literals which ↵Pete Cooper2014-08-071-2/+13
| | | | | | | | | | | | | | | are not just 0 and 1. It also allows nested { } expressions, as now that they are sized, we can merge pull bits from the nested value. In the current behaviour, everything in { } must have been convertible to a single bit. However, now that binary literals are sized, its useful to be able to initialize a range of bits. So, for example, its now possible to do bits<8> x = { 0, 1, { 0b1001 }, 0, 0b0 } llvm-svn: 215086
* Change TableGen so that binary literals such as 0b001 are now sized.Pete Cooper2014-08-073-1/+19
| | | | | | | | | | | | | | | | | Instead of these becoming an integer literal internally, they now become bits<n> values. Prior to this change, 0b001 was 1 bit long. This is confusing as clearly the user gave 3 bits. This new type holds both the literal value and the size, and so can ensure sizes match on initializers. For example, this used to be legal bits<1> x = 0b00; but now it must be written as bits<2> x = 0b00; llvm-svn: 215084
* TableGen: Change { } to only accept bits<n> entries when n == 1.Pete Cooper2014-08-071-1/+4
| | | | | | | | | | | | | | | | Prior to this change, it was legal to do something like bits<2> opc = { 0, 1 }; bits<2> opc2 = { 1, 0 }; bits<2> a = { opc, opc2 }; This involved silently dropping bits from opc and opc2 which is very hard to debug. Now the above test would be an error. Having tested with an assert, none of LLVM/clang was relying on this behaviour. Thanks to Adam Nemet for the above test. llvm-svn: 215083
* Fix a whole bunch of binary literals which were the wrong size. All were ↵Pete Cooper2014-08-076-24/+24
| | | | | | | | being silently zero extended to the correct width. The commit after this changes { } and 0bxx literals to be of type bits<n> and not int. This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us. llvm-svn: 215082
* MC: split Win64EHUnwindEmitter into a shared streamerSaleem Abdulrasool2014-08-075-61/+88
| | | | | | | | | | This changes Win64EHEmitter into a utility WinEH UnwindEmitter that can be shared across multiple architectures and a target specific bit which is overridden (Win64::UnwindEmitter). This enables sharing the section selection code across X86 and the intended use in ARM for emitting unwind information for Windows on ARM. llvm-svn: 215050
* [X86][SchedModel] Fixed missing/wrong scheduling model found by code inspection.Quentin Colombet2014-08-072-3/+3
| | | | | | | | Source: Agner Fog's Instruction tables. Related to <rdar://problem/15607571> llvm-svn: 215045
* MC X86: Accept ".att_syntax prefix" and diagnose noprefixReid Kleckner2014-08-061-1/+12
| | | | | | | | Fixes PR18916. I don't think we need to implement support for either hybrid syntax. Nobody should write Intel assembly with '%' prefixes on their registers or AT&T assembly without them. llvm-svn: 215031
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