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authorReed Kotler <rkotler@mips.com>2014-08-07 22:09:01 +0000
committerReed Kotler <rkotler@mips.com>2014-08-07 22:09:01 +0000
commit87048a4c9eb1b74548a9ab5c6c7717ae3be80bbd (patch)
treefeb54949164a98b6dee2134555fbc1c3ca2717a8 /llvm/lib
parentb9fd9ed37ebf24d0935fe597cc8ea13f77288636 (diff)
downloadbcm5719-llvm-87048a4c9eb1b74548a9ab5c6c7717ae3be80bbd.tar.gz
bcm5719-llvm-87048a4c9eb1b74548a9ab5c6c7717ae3be80bbd.zip
fix materialization of one bit constants and global values which are accessed through
a base GOT entry. Summary: get tip of tree mips fast-isel to pass test-suite Two bugs were fixed: 1) one bit booleans were treated as 1 bit signed integers and so the literal '1' could become sign extended. 2) mips uses got for pic but in certain cases, as with string constants for example, many items can be referenced from the same got entry and this case was not handled properly. Test Plan: test-suite Reviewers: dsanders Reviewed By: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D4801 llvm-svn: 215155
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/MipsFastISel.cpp12
1 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index af4c4ab69e3..6c053342b7a 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -110,7 +110,7 @@ private:
}
MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
- unsigned MemReg, int64_t MemOffset) {
+ unsigned MemReg, int64_t MemOffset) {
return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
}
@@ -353,15 +353,23 @@ unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
return 0;
EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
GV, 0, MipsII::MO_GOT);
+ if ((GV->hasInternalLinkage() ||
+ (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
+ unsigned TempReg = createResultReg(RC);
+ EmitInst(Mips::ADDiu, TempReg).addReg(DestReg).addGlobalAddress(
+ GV, 0, MipsII::MO_ABS_LO);
+ DestReg = TempReg;
+ }
return DestReg;
}
+
unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
return 0;
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
const ConstantInt *CI = cast<ConstantInt>(C);
int64_t Imm;
- if (CI->isNegative())
+ if ((VT != MVT::i1) && CI->isNegative())
Imm = CI->getSExtValue();
else
Imm = CI->getZExtValue();
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