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* Simplify the datalayout string of ARM and AArch64.Rafael Espindola2013-12-122-4/+4
| | | | | | | | No functionality change. Reviewed by Tim Northover. llvm-svn: 197172
* Simplify the SystemZ datalayout string.Rafael Espindola2013-12-121-2/+1
| | | | | | Reviewed by Richard Sandiford. llvm-svn: 197170
* Use "a" instead of "a0" in DataLayout.Rafael Espindola2013-12-123-3/+3
| | | | | | It means exactly the same and is just a bit shorter. llvm-svn: 197169
* Fix Typo.Rafael Espindola2013-12-121-1/+1
| | | | llvm-svn: 197168
* Convert the other getHostByName implementations to StringRef.Rafael Espindola2013-12-121-5/+5
| | | | llvm-svn: 197166
* Switch to the new MingW ABI.Rafael Espindola2013-12-122-5/+5
| | | | | | | GCC 4.7 changed the MingW ABI. On the LLVM side it means that sret functions don't pop the stack. llvm-svn: 197163
* [AArch64] Removed unnecessary copy patterns with v1fx types.Chad Rosier2013-12-124-27/+3
| | | | | | | | | | | | | | - Copy patterns with float/double types are enough. - Fix typos in test case names that were using v1fx. - There is no ACLE intrinsic that uses v1f32 type. And there is no conflict of neon and non-neon ovelapped operations with this type, so there is no need to support operations with this type. - Remove v1f32 from FPR32 register and disallow v1f32 as a legal type for operations. Patch by Ana Pazos! llvm-svn: 197159
* Return a StringRef from getHostCPUName.Rafael Espindola2013-12-121-1/+1
| | | | llvm-svn: 197158
* [cleanup] Remove trailing whitespace before I start changing this file.Chandler Carruth2013-12-121-1/+1
| | | | llvm-svn: 197149
* Added new X86 patterns to select SSE scalar fp arithmetic instructions fromAndrea Di Biagio2013-12-121-0/+83
| | | | | | | | | | | | | | | | | | | | | | a vector packed single/double fp operation followed by a vector insert. The effect is that the backend coverts the packed fp instruction followed by a vectro insert into a SSE or AVX scalar fp instruction. For example, given the following code: __m128 foo(__m128 A, __m128 B) { __m128 C = A + B; return (__m128) {c[0], a[1], a[2], a[3]}; } previously we generated: addps %xmm0, %xmm1 movss %xmm1, %xmm0 we now generate: addss %xmm1, %xmm0 llvm-svn: 197145
* typo in commentGabor Greif2013-12-121-2/+2
| | | | llvm-svn: 197136
* [AArch64]Fix the problem that AArch64 backend fails to select ↵Hao Liu2013-12-121-3/+37
| | | | | | scalar_to_vector of vector types having more than one element. llvm-svn: 197135
* Add missing escape characters to the new Regex::escape() functionAlp Toker2013-12-121-21/+6
| | | | | | | | | The old AddFixedStringToRegEx() it was based on got away with this for the longest time, but the problem became easy to spot after the cleanup in r197096. Also add a quick unit test to cover regex escaping. llvm-svn: 197121
* Check for null pointer before dereferencing. A careless typo on my part.Reed Kotler2013-12-121-2/+2
| | | | | | | I don't know why this did not show up earlier. This code has been around for ages. llvm-svn: 197119
* Resubmit r196544: Apply transformation on OS X 10.9+ and iOS 7.0+: pow(10, ↵Yi Jiang2013-12-122-0/+31
| | | | | | x) ―> __exp10(x) llvm-svn: 197109
* Add TargetLibraryInfo in LTO passes builderYi Jiang2013-12-121-0/+4
| | | | llvm-svn: 197105
* Remove unused multiclass from PPCInstrInfo.tdHal Finkel2013-12-121-14/+0
| | | | llvm-svn: 197100
* Improve instruction scheduling for the PPC POWER7Hal Finkel2013-12-127-3/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aside from a few minor latency corrections, the major change here is a new hazard recognizer which focuses on better dispatch-group formation on the POWER7. As with the PPC970's hazard recognizer, the most important thing it does is avoid load-after-store hazards within the same dispatch group. It uses the POWER7's special dispatch-group-terminating nop instruction (instead of inserting multiple regular nop instructions). This new hazard recognizer makes use of the scheduling dependency graph itself, built using AA information, to robustly detect the possibility of load-after-store hazards. significant test-suite performance changes (the error bars are 99.5% confidence intervals based on 5 test-suite runs both with and without the change -- speedups are negative): speedups: MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2 -0.55171% +/- 0.333168% MultiSource/Benchmarks/TSVC/CrossingThresholds-dbl/CrossingThresholds-dbl -17.5576% +/- 14.598% MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl -29.5708% +/- 7.09058% MultiSource/Benchmarks/TSVC/Reductions-flt/Reductions-flt -34.9471% +/- 11.4391% SingleSource/Benchmarks/BenchmarkGame/puzzle -25.1347% +/- 11.0104% SingleSource/Benchmarks/Misc/flops-8 -17.7297% +/- 9.79061% SingleSource/Benchmarks/Shootout-C++/ary3 -35.5018% +/- 23.9458% SingleSource/Regression/C/uint64_to_float -56.3165% +/- 25.4234% SingleSource/UnitTests/Vectorizer/gcc-loops -18.5309% +/- 6.8496% regressions: MultiSource/Benchmarks/ASCI_Purple/SMG2000/smg2000 18.351% +/- 12.156% SingleSource/Benchmarks/Shootout-C++/methcall 27.3086% +/- 14.4733% llvm-svn: 197099
* Fix an over-constrained assertion in MachineFunction::addLiveIn.Quentin Colombet2013-12-121-1/+10
| | | | | | | | | | | | | | | | The assertion was checking that the virtual register VReg used to represent the physical register PReg uses the same register class as the one passed to MachineFunction::addLiveIn. This is over-constraining because it is sufficient to check that the register class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and that VRegRC contains PReg. Indeed, if VReg gets constrained because of some operation constraints between two calls of MachineFunction::addLiveIn, the original assertion cannot match. This fixes <rdar://problem/15633429>. llvm-svn: 197097
* Expose FileCheck's AddFixedStringToRegEx as Regex::escapeHans Wennborg2013-12-121-0/+29
| | | | | | | Both FileCheck and clang's -verify need to escape strings for regexes, so let's expose this as a utility in the Regex class. llvm-svn: 197096
* [AArch64] Refactor NEON floating-point Max/Min/Maxnm/Minnm across vector AArch64Chad Rosier2013-12-111-2/+2
| | | | | | intrinsics to use f32 types, rather than their vector equivalents. llvm-svn: 197090
* Fix the PPC subsumes-predicate checkHal Finkel2013-12-111-0/+4
| | | | | | | | | For one predicate to subsume another, they must both check the same condition register. Failure to check this prerequisite was causing miscompiles. Fixes PR18003. llvm-svn: 197089
* Add two additional hazard recognizer functionsHal Finkel2013-12-111-7/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds two additional functions to the hazard recognizer interface. These are optional (in the sense that the default implementations preserve the current behavior), and used by the post-RA scheduler. Upcoming commits will use this functionality in order to improve dispatch-group formation on the POWER7 and related cores. Dispatch groups are an odd construct: sometimes we need to insert nops to force a new one to start (for performance reasons), and some instructions need to appear in certain positions within a group, but the groups are not fundamentally cycle based (they can contain instructions with data dependencies with non-trivial latencies). Motivation: unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert nops to force a new dispatch group to begin. We already have a NoopHazard, and this is also still needed. However, NoopHazard only causes a nop to be inserted if there are no other available instructions, and so is not always sufficient. The number of nops to insert depends on state that only the hazard recognizer has, so a general callback is necessary. bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that would start a new dispatch group when others are available that could be part of the current dispatch group. In this case, we don't want to issue nops, because the non-preferred instruction will implicitly start a new dispatch group regardless. Although the motivation for these functions is driven by the PowerPC backend, they are completely general. llvm-svn: 197084
* On ELF and COFF treat linker_private like private.Rafael Espindola2013-12-111-1/+1
| | | | | | | | The linkers on these systems don't have anything special to do with these symbols. Since the intent is for them to be absent from the final object, just treat them as private. llvm-svn: 197080
* Revert "DebugInfo: Move type units into the debug_types section with ↵David Blaikie2013-12-114-57/+9
| | | | | | | | | | | | appropriate comdat grouping and type unit headers" This reverts commit r197073. The test seems to be failing on some buildbots for unknown reasons. Reverting until I can figure that out. If anyone's got a reproduction (.s and .o together would be great) - I'd really appreciate it. llvm-svn: 197079
* DebugInfo: Move type units into the debug_types section with appropriate ↵David Blaikie2013-12-114-9/+57
| | | | | | | | | | | comdat grouping and type unit headers This commit does not complete the type units feature - there are issues around fission support (skeletal type units, pubtypes/pubnames) and hashing of some types including those containing references to types in other type units. llvm-svn: 197073
* DwarfUnit: LLVM_OVERRIDE and constify some functionsDavid Blaikie2013-12-112-4/+4
| | | | llvm-svn: 197072
* [AArch64] Add NEON scalar floating-point compare LLVM AArch64 intrinsics thatChad Rosier2013-12-111-16/+18
| | | | | | use f32/f64 types, rather than their vector equivalents. llvm-svn: 197068
* [AArch64] Refactor the NEON scalar floating-point reciprocal step andChad Rosier2013-12-111-11/+11
| | | | | | | floating-point reciprocal square root step LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197067
* [AArch64] Refactor the NEON scalar floating-point reciprocal estimate, floating-Chad Rosier2013-12-111-10/+19
| | | | | | | | point reciprocal exponent, and floating-point reciprocal square root estimate LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197066
* Don't set unused variable.Rafael Espindola2013-12-111-1/+0
| | | | llvm-svn: 197064
* R600: Re-format Processors.tdTom Stellard2013-12-111-0/+48
| | | | | | | This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
* R600: Register AMDGPUCFGStructurizer passTom Stellard2013-12-113-10/+23
| | | | | | | This enables -print-before-all to dump MachineInstrs after it is run. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197057
* R600: Register R600EmitClauseMarkers passTom Stellard2013-12-113-9/+19
| | | | | | | This enables -print-before-all to dump MachineInstrs after it is run. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197056
* [arm] Implement ARM .arch directive.Logan Chien2013-12-114-2/+223
| | | | llvm-svn: 197052
* SelectionDAG: Fix a typo.Benjamin Kramer2013-12-111-1/+1
| | | | | | Found by "cppcheck". PR18208. llvm-svn: 197047
* ARM: constrain register-class in fast-iselTim Northover2013-12-111-1/+3
| | | | | | | | The tests were no longer using fast-isel at all (MachO needs an "ios" rather than "darwin" triple at the moment and Linux needs ARM mode). Once that was corrected, the verifier complained about a t2ADDri created for the alloca. llvm-svn: 197046
* Build fix for Android NDK which has neither futimes nor futimensAlp Toker2013-12-111-3/+6
| | | | | | Based on a patch by Neil Henning! llvm-svn: 197045
* AVX-512: Removed "z" suffix from AVX-512 instructions, since it is ↵Elena Demikhovsky2013-12-112-99/+102
| | | | | | | | | incompatible with GCC. I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). llvm-svn: 197041
* [SystemZ] Optimize fcmp X, 0 in cases where X is also negatedRichard Sandiford2013-12-111-4/+30
| | | | | | | In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
* Extend (truncate (load)) foldingRichard Sandiford2013-12-111-0/+14
| | | | | | | | | DAGCombiner could fold (truncate (load)) -> smaller load if the original load was the width of the truncation result or wider. This patch extends it to handle cases where the original load was narrower (and so the extension type stays the same). llvm-svn: 197030
* Add TargetRegisterInfo::reverseLocalAssignment hook.Andrew Trick2013-12-111-1/+8
| | | | | | | | | | | | | | This hook reverses the order of assignment for local live ranges. This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It should still achieve optimal coloring; however, it can change register eviction decisions. It is disabled by default for two reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. llvm-svn: 197001
* Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.Reed Kotler2013-12-112-4/+16
| | | | llvm-svn: 196999
* [AArch64 NEON] Get instruction BSL matched to VSELECT.Kevin Qin2013-12-113-24/+17
| | | | llvm-svn: 196998
* Move mips' datalayout computation out of line and add comments.Rafael Espindola2013-12-111-11/+31
| | | | llvm-svn: 196996
* Move Sparc's getDataLayout out of line and add comments.Rafael Espindola2013-12-112-10/+24
| | | | llvm-svn: 196990
* Prune redundant dependencies in LLVMBuild.txt.NAKAMURA Takumi2013-12-1128-28/+28
| | | | llvm-svn: 196988
* Move PPC's getDataLayoutString out of line and document it better.Rafael Espindola2013-12-112-17/+39
| | | | llvm-svn: 196987
* Revert the backend fatal error from r196939Reid Kleckner2013-12-101-6/+0
| | | | | | | | | | | | | | The combination of inline asm, stack realignment, and dynamic allocas turns out to be too common to reject out of hand. ASan inserts empy inline asm fragments and uses aligned allocas. Compiling any trivial function containing a dynamic alloca with ASan is enough to trigger the check. XFAIL the test cases that would be miscompiled and add one that uses the relevant functionality. llvm-svn: 196986
* Refactor the computation of the x86 datalayout.Rafael Espindola2013-12-101-14/+47
| | | | llvm-svn: 196976
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