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* [X86] Restrict max long nop length for Lakemont.Andrey Turetskiy2016-04-111-1/+2
| | | | | | | | | Restrict the max length of long nops for Lakemont to 7. Experiments on MCU benchmarks (Dhrystone, Coremark) show that this is the most optimal length. Differential Revision: http://reviews.llvm.org/D18897 llvm-svn: 265924
* [IndVars] Eliminate op.with.overflow when possibleSanjoy Das2016-04-101-0/+107
| | | | | | | | | | | | | | | Summary: If we can prove that an op.with.overflow intrinsic does not overflow, we can get rid of the intrinsic, and replace it with non-wrapping arithmetic. Reviewers: atrick, regehr Subscribers: sanjoy, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18685 llvm-svn: 265913
* [SCEV] See through op.with.overflow intrinsicsSanjoy Das2016-04-102-5/+110
| | | | | | | | | | | | | | | Summary: This change teaches SCEV to see reduce `(extractvalue 0 (op.with.overflow X Y))` into `op X Y` (with a no-wrap tag if possible). Reviewers: atrick, regehr Subscribers: mcrosier, mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D18684 llvm-svn: 265912
* Plumb the option to emit the `ModuleHash` in the bitcode through the bitcode ↵Mehdi Amini2016-04-101-6/+7
| | | | | | | writer APIs From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265907
* [X86][AVX512BW] Add support for v64i8 multipliesSimon Pilgrim2016-04-101-3/+38
| | | | | | | | | | Extend the existing lowering of vXi8 multiplies to support v64i8 on avx512bw targets. I added the Lower512IntArith helper function to help with this - not sure how often this could be used in the future, but it seemed better than putting all that logic inside LowerMUL. Differential Revision: http://reviews.llvm.org/D18937 llvm-svn: 265902
* Loop vectorization with uniform loadElena Demikhovsky2016-04-101-0/+9
| | | | | | | | | Vectorization cost of uniform load wasn't correctly calculated. As a result, a simple loop that loads a uniform value wasn't vectorized. Differential Revision: http://reviews.llvm.org/D18940 llvm-svn: 265901
* [ThinLTO] Remove unused parameter (NFC)Teresa Johnson2016-04-101-9/+7
| | | | llvm-svn: 265900
* [X86] Use for loops over types to reduce code for setting up operation actions.Craig Topper2016-04-101-150/+97
| | | | llvm-svn: 265893
* [X86] Remove unnecessary setOperationAction for SRA v2i64/v4i64 when VLX is ↵Craig Topper2016-04-101-2/+0
| | | | | | suppored. This is already done for SSE2/AVX2 which VLX implies. NFC llvm-svn: 265892
* [PGO] Fix deserialize bug Xinliang David Li2016-04-101-1/+3
| | | | | | | | | | Raw function pointer collected by value profile data may be from external functions that are not instrumented. They won't have mapping data to be used by the deserializer. Force the value to be 0 in this case. llvm-svn: 265890
* [CodeGen] Don't assume that fixed stack objects are aligned in a ↵Charles Davis2016-04-091-5/+16
| | | | | | | | | | | | | | | | | | | | stack-realigned function. Summary: After we make the adjustment, we can assume that for local allocas, but not for stack parameters, the return address, or any other fixed stack object (which has a negative offset and therefore lies prior to the adjusted SP). Fixes PR26662. Reviewers: hfinkel, qcolombet, rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D18471 llvm-svn: 265886
* [MC] support TLSDESC and TLSCALL / GNU2 tls dialectDavide Italiano2016-04-091-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18885 llvm-svn: 265881
* Drop debug info for DISubprograms that are not referenced by anythingAdrian Prantl2016-04-094-53/+8
| | | | | | | | | | | | | | | | | | | | | This patch drops the debug info for all DISubprograms that are (a) not attached to an llvm::Function and (b) not indirectly reachable via inline scopes from any surviving Function and (c) not reachable from a type (i.e.: member functions). Background: I'm currently working on a patch to reverse the pointers between DICompileUnit and DISubprogram (for more info check Duncan's RFC on lazy-loading of debug info metadata http://lists.llvm.org/pipermail/llvm-dev/2016-March/097419.html). The idea is to remove the list of subprograms from DICompileUnit and instead point to the owning compile unit from each DISubprogram. After doing this all DISubprograms fulfilling the above criteria will be implicitly dropped unless we go through an extra effort to preserve them. http://reviews.llvm.org/D18477 <rdar://problem/25256815> llvm-svn: 265876
* [x86] use BMI 'andn' for logic + compare ops Sanjay Patel2016-04-092-3/+17
| | | | | | | | | | With BMI, we can use 'andn' to save an instruction when the result is only used in a compare. This is related to one of the potential sequences to check 'isfinite' in: https://llvm.org/bugs/show_bug.cgi?id=27164 Differential Revision: http://reviews.llvm.org/D18910 llvm-svn: 265875
* [X86][XOP] Support for VPPERM 2-input shuffle mask decodingSimon Pilgrim2016-04-093-27/+127
| | | | | | | | | | This patch adds support for decoding XOP VPPERM instruction when it represents a basic shuffle. The mask decoding required the existing MCInstrLowering code to be updated to support binary shuffles - the implementation now matches what is done in X86InstrComments.cpp. Differential Revision: http://reviews.llvm.org/D18441 llvm-svn: 265874
* [X86] Use for loops over types to reduce code for setting up operation ↵Craig Topper2016-04-091-149/+78
| | | | | | actions. NFC llvm-svn: 265871
* [X86] Remove calls to setOperationAction that set CTLZ_ZERO_UNDEF for some ↵Craig Topper2016-04-091-16/+0
| | | | | | vector types to Expand. Expand is already set for all operations for all vector types earlier so this is redundant. NFC llvm-svn: 265870
* Maintain calling convention when inling calls to llvm.deoptimizeSanjoy Das2016-04-091-1/+3
| | | | | | | The behavior here was buggy -- we'd forget the calling convention after inlining a callsite calling llvm.deoptimize. llvm-svn: 265867
* [libfuzzer] defensive assertMike Aizatsky2016-04-081-1/+2
| | | | llvm-svn: 265866
* Support the Nodebug emission kind for DICompileUnits.Adrian Prantl2016-04-084-55/+66
| | | | | | | | | | | | | | | | Sample-based profiling and optimization remarks currently remove DICompileUnits from llvm.dbg.cu to suppress the emission of debug info from them. This is somewhat of a hack and only borderline legal IR. This patch uses the recently introduced NoDebug emission kind in DICompileUnit to achieve the same result without breaking the Verifier. A nice side-effect of this change is that it is now possible to combine NoDebug and regular compile units under LTO. http://reviews.llvm.org/D18808 <rdar://problem/25427165> llvm-svn: 265861
* Refactor Threshold computation. NFC.Easwaran Raman2016-04-081-22/+35
| | | | | | This is part of changes reviewed in http://reviews.llvm.org/D17584. llvm-svn: 265852
* [SSP] Remove llvm.stackprotectorcheck.Tim Shen2016-04-0810-132/+109
| | | | | | | | | | This is a cleanup patch for SSP support in LLVM. There is no functional change. llvm.stackprotectorcheck is not needed, because SelectionDAG isn't actually lowering it in SelectBasicBlock; rather, it adds check code in FinishBasicBlock, ignoring the position where the intrinsic is inserted (See FindSplitPointForStackProtector()). llvm-svn: 265851
* Rangeify a loop. NFC.Hans Wennborg2016-04-081-4/+3
| | | | llvm-svn: 265846
* Remove some redundant variables from X86TargetLowering::LowerDYNAMIC_STACKALLOCHans Wennborg2016-04-081-3/+0
| | | | | | These are already defined, with the same values, a few lines up. NFC. llvm-svn: 265845
* Codegen: Factor tail duplication into a utility class. NFCKyle Butt2016-04-083-949/+923
| | | | | | | | | | | This is in preparation for tail duplication during block placement. See D18226. This needs to be a utility class for 2 reasons. No passes may run after block placement, and also, tail-duplication affects subsequent layout decisions, so it must be interleaved with placement, and can't be separated out into its own pass. The original pass is still useful, and now runs by delegating to the utility class. llvm-svn: 265842
* test commitEvgeny Stupachenko2016-04-081-2/+2
| | | | llvm-svn: 265840
* Fix Load Control Dependence in MemCpy GenerationNirav Dave2016-04-082-57/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Memcpy lowering we had missed a dependence from the load of the operation to successor operations. This causes us to potentially construct an in initial DAG with a memory dependence not fully represented in the chain sub-DAG but rather require looking at the entire DAG breaking alias analysis by allowing incorrect repositioning of memory operations. To work around this, r200033 changed DAGCombiner::GatherAllAliases to be conservative if any possible issues to happen. Unfortunately this check forbade many non-problematic situations as well. For example, it's common for incoming argument lowering to add a non-aliasing load hanging off of EntryNode. Then, if GatherAllAliases visited EntryNode, it would find that other (unvisited) use of the EntryNode chain, and just give up entirely. Furthermore, the check was incomplete: it would not actually detect all such potentially problematic DAG constructions, because GatherAllAliases did not guarantee to visit all chain nodes going up to the root EntryNode. This is in general fine -- giving up early will just miss a potential optimization, not generate incorrect results. But, for this non-chain dependency detection code, it's possible that you could have a load attached to a higher-up chain node than any which were visited. If that load aliases your store, but the only dependency is through the value operand of a non-aliasing store, it would've been missed by this code, and potentially reordered. With the dependence added, this check can be removed and Alias Analysis can be much more aggressive. This fixes code quality regression in the Consecutive Store Merge cleanup (D14834). Test Change: ppc64-align-long-double.ll now may see multiple serializations of its stores Differential Revision: http://reviews.llvm.org/D18062 llvm-svn: 265836
* ValueMapper: Extract llvm::RemapFunction from IRMover.cpp, NFCDuncan P. N. Exon Smith2016-04-082-25/+38
| | | | | | | | | | | | | | Strip out the remapping parts of IRLinker::linkFunctionBody and put them in ValueMapper.cpp under the name Mapper::remapFunction (with a top-level entry-point llvm::RemapFunction). This is a nice cleanup on its own since it puts the remapping code together and shares a single Mapper context for the entire IRLinker::linkFunctionBody Call. Besides that, this will make it easier to break the co-recursion between IRMover.cpp and ValueMapper.cpp in follow ups. llvm-svn: 265835
* ValueMapper: Always use Mapper::mapValue from remapInstruction, NFCIDuncan P. N. Exon Smith2016-04-081-2/+1
| | | | | | | | | | | | Use Mapper::mapValue instead of llvm::MapValue from Mapper::remapInstruction when mapping an incoming block for a PHINode (follow-up to r265832). This will implicitly pass along the Materializer argument, but when this code was added in r133513 there was no Materializer argument. I suspect this call to MapValue was just missed in r182776 since it's not observable (basic blocks can't be materialized, and they don't reference other values). llvm-svn: 265833
* ValueMapper: Roll RemapInstruction into Mapper, NFCDuncan P. N. Exon Smith2016-04-081-8/+11
| | | | | | | | | | | | Add Mapper::remapInstruction, move the guts of llvm::RemapInstruction into it, and use the same Mapper for most of the calls to MapValue and MapMetadata. There should be no functionality change here. I left off the call to MapValue that wasn't passing in a Materializer argument (for basic blocks of PHINodes). It shouldn't change functionality either, but I'm suspicious enough to commit separately. llvm-svn: 265832
* Linker: Always pass RF_IgnoreMissingLocals; NFCDuncan P. N. Exon Smith2016-04-081-3/+3
| | | | | | | | | | | This is a cleanup after clarifying the meaning of RF_IgnoreMissingLocals in r265628 and truly limiting it to locals in r265768. This should have no functionality change, since the only context that the flag has an effect is when we could hit function-local Value and Metadata, and we were already passing it in those contexts. llvm-svn: 265831
* [X86] Fix PR23155 by turning on X86FixupBWInsts by default.Kevin B. Smith2016-04-081-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D18866 llvm-svn: 265830
* ValueMapper: Don't memoize metadata when RF_NoModuleLevelChangesDuncan P. N. Exon Smith2016-04-081-1/+1
| | | | | | | | | Prevent the Metadata side-table in ValueMap from growing unnecessarily when RF_NoModuleLevelChanges. As a drive-by, make ValueMap::hasMD, which apparently had no users until I used it here for testing, actually compile. llvm-svn: 265828
* ValueMapper: Stop memoizing MDStringsDuncan P. N. Exon Smith2016-04-081-2/+6
| | | | | | | | | | | | | | | Stop adding MDString to the Metadata section of the ValueMap in MapMetadata. It blows up the size of the map for no benefit, since we can always return quickly anyway. There is a potential follow-up that I don't think I'll push on right away, but maybe someone else is interested: stop checking for a pre-mapped MDString, and move the `isa<MDString>()` checks in Mapper::mapSimpleMetadata and MDNodeMapper::getMappedOp in front of the `VM.getMappedMD()` calls. While this would preclude explicitly remapping MDStrings it would probably be a little faster. llvm-svn: 265827
* Propagate Undef in llvm.cos IntrinsicSanjoy Das2016-04-081-0/+5
| | | | | | | | | | | | | | | | | | Summary: The llvm cos intrinsic currently does not propagate undef's. This change transforms cos(undef) to null value or 0. There are 2 test cases added as well. Patch by Anna Thomas! Reviewers: sanjoy Subscribers: majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D18863 llvm-svn: 265825
* [Object] Report an error if .alt_entry is used with ELF or COFF.Lang Hames2016-04-082-1/+3
| | | | | | | I'm looking into a better way to do this long-term, but for now at least don't crash. llvm-svn: 265815
* [SystemZ] Support conditional sibling calls via BRCLUlrich Weigand2016-04-083-1/+26
| | | | | | | | | | | | This adds a conditional variant of CallJG instruction, CallBRCL. It can be used for conditional sibling calls. Unfortunately, due to IfCvt limitations, it only really works well for functions without arguments. Author: koriakin Differential Revision: http://reviews.llvm.org/D18864 llvm-svn: 265814
* [RegBankSelect] Use reverse post order traversal.Quentin Colombet2016-04-081-2/+12
| | | | | | | | When assigning the register banks of an instruction, it is best to know all the constraints of the input to have a good idea of how this will impact the cost of the whole function. llvm-svn: 265812
* [RegisterBankInfo] Change the implementation for the default mapping.Quentin Colombet2016-04-081-1/+14
| | | | | | | | | | Do not give that much importance to the current register bank of an operand. This is likely just a side effect of the current execution and it is properly wise to prefer a register bank that can be extracted from the information available statically (like encoding constraints and type). llvm-svn: 265810
* [InstCombine] Fix miscompile in FoldSPFofSPFDavid Majnemer2016-04-081-0/+3
| | | | | | | | | | | We had a select of a cast of a select but attempted to replace the outer select with the inner select dispite their incompatible types. Patch by Anton Korobeynikov! This fixes PR27236. llvm-svn: 265805
* [RegBankSelect] Improve debug output.Quentin Colombet2016-04-081-1/+10
| | | | | | | | Add verbose information when checking if the current and the desired register banks match. Detail what happens when we assign a register bank. llvm-svn: 265804
* Fix missing include on OpenBSDMehdi Amini2016-04-081-0/+1
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265803
* [MIR] Teach the parser how to deal with register banks.Quentin Colombet2016-04-081-10/+51
| | | | llvm-svn: 265802
* [InstCombine] Add a peephole for redundant assumesDavid Majnemer2016-04-081-2/+7
| | | | | | | | | | Two or more identical assumes are occasionally next to each other in a basic block. While our generic machinery will turn a redundant assume into a no-op, it is not super cheap. We can perform a simpler check to achieve the same result for this case. llvm-svn: 265801
* [LoopVectorize] Register cloned assumptionsDavid Majnemer2016-04-081-10/+24
| | | | | | | | | | | | InstCombine cannot effectively remove redundant assumptions without them registered in the assumption cache. The vectorizer can create identical assumptions but doesn't register them with the cache, resulting in slower compile times because InstCombine tries to reason about a lot more assumptions. Fix this by registering the cloned assumptions. llvm-svn: 265800
* [MachineVerifier] Teach how to check some of the properties of genericQuentin Colombet2016-04-081-1/+24
| | | | | | | | | | | | | | virtual registers. Generic virtual registers: - May not have a register class - May not have a register bank - If they do not have a register class they must have a size - If they have a register bank, the size of the register bank must be greater or equal to the size of the virtual register (basically check that the virtual register will fit into that register class) llvm-svn: 265798
* [MIR] Teach the mir printer how to print the register bank.Quentin Colombet2016-04-081-5/+8
| | | | | | | | | For now, we put the register bank in the Class field since a register may only have one of those at a given time. The downside of that representation is that if a register class and a register bank have the same name, we will not be able to distinguish them. llvm-svn: 265796
* [ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selectionSam Parker2016-04-081-0/+138
| | | | | | | | | | Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
* Revert r265547 "Recommit r265309 after fixed an invalid memory reference bug ↵Hans Wennborg2016-04-0810-722/+526
| | | | | | | | | | | | | happened" It caused PR27275: "ARM: Bad machine code: Using an undefined physical register" Also reverting the following commits that were landed on top: r265610 "Fix the compare-clang diff error introduced by r265547." r265639 "Fix the sanitizer bootstrap error in r265547." r265657 "InlineSpiller.cpp: Escap \@ in r265547. [-Wdocumentation]" llvm-svn: 265790
* Re-commit [SCEV] Introduce a guarded backedge taken count and use it in LAA ↵Silviu Baranga2016-04-084-91/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and LV This re-commits r265535 which was reverted in r265541 because it broke the windows bots. The problem was that we had a PointerIntPair which took a pointer to a struct allocated with new. The problem was that new doesn't provide sufficient alignment guarantees. This pattern was already present before r265535 and it just happened to work. To fix this, we now separate the PointerToIntPair from the ExitNotTakenInfo struct into a pointer and a bool. Original commit message: Summary: When the backedge taken codition is computed from an icmp, SCEV can deduce the backedge taken count only if one of the sides of the icmp is an AddRecExpr. However, due to sign/zero extensions, we sometimes end up with something that is not an AddRecExpr. However, we can use SCEV predicates to produce a 'guarded' expression. This change adds a method to SCEV to get this expression, and the SCEV predicate associated with it. In HowManyGreaterThans and HowManyLessThans we will now add a SCEV predicate associated with the guarded backedge taken count when the analyzed SCEV expression is not an AddRecExpr. Note that we only do this as an alternative to returning a 'CouldNotCompute'. We use new feature in Loop Access Analysis and LoopVectorize to analyze and transform more loops. Reviewers: anemet, mzolotukhin, hfinkel, sanjoy Subscribers: flyingforyou, mcrosier, atrick, mssimpso, sanjoy, mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D17201 llvm-svn: 265786
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