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* [X86] Rename some instructions so that 'b' is added as a suffix instead of ↵Craig Topper2017-12-103-22/+22
| | | | | | replacing an 'r' llvm-svn: 320290
* [X86] Add CMPSDrr/rm to the scheduler models.Craig Topper2017-12-105-0/+10
| | | | | | Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing. llvm-svn: 320289
* PowerPC: support external pid instructions in MC layer.Tim Northover2017-12-101-0/+57
| | | | | | | | | | | This adds assembly & disassembly support for the e500mc "external pid" instructions. See https://reviews.llvm.org/D39249. Patch by vit9696 <vit9696@avp.su> llvm-svn: 320287
* [PGO] change arg type to uint64_t to match member field typeXinliang David Li2017-12-101-2/+2
| | | | llvm-svn: 320285
* [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since ↵Craig Topper2017-12-103-20/+20
| | | | | | they can only be selected by intrinsics. llvm-svn: 320283
* [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the ↵Craig Topper2017-12-101-78/+78
| | | | | | correct order relative to _Int llvm-svn: 320282
* [X86] Remove ReadAfterLd from several several rb instructionsCraig Topper2017-12-101-5/+5
| | | | | | | | This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions 'b' here refers to 'sae' not broadcast. These aren't memory instructions. llvm-svn: 320281
* [X86] Fix bad regular expressions in the scheduler models. Question marks ↵Craig Topper2017-12-104-239/+231
| | | | | | | | | | should be outside of multicharacter parenthesized expressions If the question mark is inside the parentheses it only applies to the single character proceeding it. I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this. llvm-svn: 320279
* [X86] Make the _Int part of some instregex sheduler patterns optionalCraig Topper2017-12-101-8/+8
| | | | llvm-svn: 320278
* [X86] Add the commutable floating point min/max pseudo instructions to ↵Craig Topper2017-12-104-160/+160
| | | | | | sandybridge,haswell,broadwell,skylakeclient scheduler models. llvm-svn: 320277
* [X86] Tag PIC setup instruction as jump scheduler classSimon Pilgrim2017-12-101-2/+3
| | | | llvm-svn: 320276
* [X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classesSimon Pilgrim2017-12-101-3/+5
| | | | | Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions llvm-svn: 320275
* [X86] Tag TLS instructions as system scheduler classesSimon Pilgrim2017-12-101-1/+2
| | | | llvm-svn: 320274
* [X86] Tag ALLOCA/VAARG instructions as system scheduler classesSimon Pilgrim2017-12-101-0/+2
| | | | llvm-svn: 320273
* [AArch64] Improve loop unrolling performance on Cavium T99Joel Jones2017-12-091-1/+1
| | | | | | | | | | | | | | | | | This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4): https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file, loop unrolling becomes more aggressive. This helps performance on T99. Test case included. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D40695 llvm-svn: 320272
* [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)Simon Pilgrim2017-12-091-6/+5
| | | | | | Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.) llvm-svn: 320270
* Infer lowest bits of an integer Multiply when the low bits of the operands ↵Simon Dardis2017-12-091-9/+66
| | | | | | | | | | | | | | | are known When the lowest bits of the operands to an integer multiply are known, the low bits of the result are deducible. Code to deduce known-zero bottom bits already existed, but this change improves on that by deducing known-ones. Patch by: Pedro Ferreira Reviewers: craig.topper, sanjoy, efriedma Differential Revision: https://reviews.llvm.org/D34029 llvm-svn: 320269
* [X86] Use KMOV instructions to zero upper bits of vectors when possible.Craig Topper2017-12-091-12/+29
| | | | llvm-svn: 320268
* [X86] Improve lowering of vXi1 insert_subvectors to better utilize ↵Craig Topper2017-12-091-67/+87
| | | | | | | | (insert_subvector zero, vec, 0) for zeroing upper bits. This can be better recognized during isel when the producer already zeroed the upper bits. llvm-svn: 320267
* [X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classesSimon Pilgrim2017-12-091-3/+7
| | | | llvm-svn: 320266
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-092-13/+13
| | | | llvm-svn: 320265
* [X86] Tag FS/GS BASE R/W instruction scheduler classesSimon Pilgrim2017-12-092-9/+18
| | | | llvm-svn: 320264
* [X86] Tag REP/REPNE prefix instructions as microcoded scheduler classesSimon Pilgrim2017-12-091-3/+2
| | | | llvm-svn: 320263
* [X86] Tag missing EH pseudo instruction scheduler classesSimon Pilgrim2017-12-092-3/+4
| | | | llvm-svn: 320262
* [X86] Tag frame pointer XORs instruction scheduler classesSimon Pilgrim2017-12-091-2/+4
| | | | llvm-svn: 320261
* [X86] Don't use getTargetConstant for all 0s and all 1s mask vector.Craig Topper2017-12-091-10/+8
| | | | llvm-svn: 320260
* [X86] Tag segment prefixes as NOP instruction scheduling classesSimon Pilgrim2017-12-091-7/+8
| | | | llvm-svn: 320257
* [X86][AVX512] Drop a default NoItinerary argument that isn't used any more. ↵Simon Pilgrim2017-12-091-6/+6
| | | | | | | | NFCI. Requires re-ordering of AVX512_maskable_custom arguments. llvm-svn: 320255
* Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. ↵Simon Pilgrim2017-12-091-1/+1
| | | | | | NFCI. llvm-svn: 320254
* Fix signed/unsigned gcc warning. NFCI.Simon Pilgrim2017-12-091-1/+1
| | | | llvm-svn: 320253
* [InlineFunction] Set debug loc for call to forward varargs.Florian Hahn2017-12-091-0/+1
| | | | | | | | | | | | Reviewers: aprantl, dblaikie, rnk Reviewed By: rnk Subscribers: eraman, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D40432 llvm-svn: 320252
* [X86] When inserting into the upper bits of a vXi1 vector, make sure we ↵Craig Topper2017-12-091-1/+2
| | | | | | | | | | shift enough bits if we widened the vector. We may need to widen the vector to make the shifts legal, but if we do that we need to make sure we shift left/right after accounting for the new size. If not we can't guarantee we are shifting in zeros. The test cases affected actually show cases where we should move the shifts all together, but that's another problem. llvm-svn: 320248
* Revert and accidentally committed revert commitDylan McKay2017-12-0912-22/+285
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-0912-285/+22
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* [X86] Improve lowering of concats of mask vectors to better optimize zero ↵Craig Topper2017-12-091-59/+44
| | | | | | | | vector inputs. We were previously using kunpck with zero inputs unnecessarily. And we had cases where we would insert into a zero vector and then insert into larger zero vector incurring two sets of shifts. llvm-svn: 320244
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-093-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This relaxes an assertion inside SelectionDAGBuilder which is overly restrictive on targets which have no concept of alignment (such as AVR). In these architectures, all types are aligned to 8-bits. After this, LLVM will only assert that accesses are aligned on targets which actually require alignment. This patch follows from a discussion on llvm-dev a few months ago http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html Reviewers: bogner, nemanjai, joerg, efriedma Reviewed By: efriedma Subscribers: efriedma, cactus, llvm-commits Differential Revision: https://reviews.llvm.org/D39946 llvm-svn: 320243
* [MachineOutliner] Outline callsJessica Paquette2017-12-091-4/+118
| | | | | | | | | | | | | The outliner previously would never outline calls. Calls are pretty common in files, so it makes sense to outline them. In fact, in the LLVM test suite, if you count the number of instructions that the outliner misses when you outline calls vs when you don't, it turns out that, on average, around 6% of the instructions encountered are calls. So, if we outline calls, we can find more candidates, and thus save some more space. This commit adds that functionality and updates the mir test to reflect that. llvm-svn: 320229
* Register NetBSD/x86_64 in MemorySanitizer.cppKamil Rytarowski2017-12-091-0/+22
| | | | | | | | | | | | | | | | | | | Summary: Reuse the Linux new mapping as it is. Sponsored by <The NetBSD Foundation> Reviewers: joerg, eugenis, vitalybuka Reviewed By: vitalybuka Subscribers: llvm-commits, #sanitizers Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D41022 llvm-svn: 320219
* Hardware-assisted AddressSanitizer (llvm part).Evgeniy Stepanov2017-12-0916-15/+322
| | | | | | | | | | | | | | | | | | | | | Summary: This is LLVM instrumentation for the new HWASan tool. It is basically a stripped down copy of ASan at this point, w/o stack or global support. Instrumenation adds a global constructor + runtime callbacks for every load and store. HWASan comes with its own IR attribute. A brief design document can be found in clang/docs/HardwareAssistedAddressSanitizerDesign.rst (submitted earlier). Reviewers: kcc, pcc, alekseyshl Subscribers: srhines, mehdi_amini, mgorny, javed.absar, eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D40932 llvm-svn: 320217
* Fix out-of-order stepping behavior in programs with sunk instructions.Paul Robinson2017-12-091-1/+11
| | | | | | | | | | | | | | | | | | | MachineSink attempts to place instructions near the basic blocks where they are needed. Once an instruction has been sunk, its location relative to other instructions no longer is consistent with the original source code. In order to ensure correct stepping in the debugger, the debug location for sunk instructions is either merged with the insertion point or erased if the target successor block is empty. Originally submitted as r318679, revised to fix sanitizer failure and improve testing. Patch by Matthew Voss! Differential Revision: https://reviews.llvm.org/D39933 llvm-svn: 320216
* dwarfdump: Add support for the --diff option.Adrian Prantl2017-12-082-21/+29
| | | | | | | | | --diff Emit the output in a diff-friendly way by omitting offsets and addresses. <rdar://problem/34502625> llvm-svn: 320214
* [X86][Mips] Remove unused method declaration from the X86 and Mips AsmPrinters.Craig Topper2017-12-082-7/+0
| | | | | | Both had a declaration of EmitXRayTable, but there is no method defined in either with that name. There is a emitXRayTable in the base class with a lower case 'e' and they both call that. llvm-svn: 320213
* [CodeGen] Move printing MO_Immediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-083-9/+21
| | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Add support for operand subreg index as an immediate to debug printing and use ::print in the MIRPrinter. Differential Review: https://reviews.llvm.org/D40965 llvm-svn: 320209
* [AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp ↵Abderrazek Zaafrani2017-12-082-1/+1
| | | | | | | | to reflect the recently added features. The name change is dicsussed in https://reviews.llvm.org/D38196 llvm-svn: 320204
* Generalize llvm::replaceDbgDeclare and actually support the use-case thatAdrian Prantl2017-12-087-12/+25
| | | | | | is mentioned in the documentation (inserting a deref before the plus_uconst). llvm-svn: 320203
* [CodeExtractor] Add debug locations for new call and branch instrs.Florian Hahn2017-12-081-1/+24
| | | | | | | | | | | | | | | | | | | | | | | Summary: If a partially inlined function has debug info, we have to add debug locations to the call instruction calling the outlined function. We use the debug location of the first instruction in the outlined function, as the introduced call transfers control to this statement and there is no other equivalent line in the source code. We also use the same debug location for the branch instruction added to jump from artificial entry block for the outlined function, which just jumps to the first actual basic block of the outlined function. Reviewers: davide, aprantl, rriddle, dblaikie, danielcdh, wmi Reviewed By: aprantl, rriddle, danielcdh Subscribers: eraman, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D40413 llvm-svn: 320199
* [WebAssembly] Reapply r319186: "Support bitcasted function addresses with ↵Dan Gohman2017-12-081-1/+1
| | | | | | | | | varargs." This puts the functionality under control of a command-line option which is off by default to avoid breaking existing setups. llvm-svn: 320197
* [WebAssemby] Re-apply r320041: "Support main functions with alternate ↵Dan Gohman2017-12-081-1/+50
| | | | | | | | | | signatures." This includes a fix so that it doesn't transform declarations, and it puts the functionality under control of a command-line option which is off by default to avoid breaking existing setups. llvm-svn: 320196
* [AArch64] Add Exynos to host detectionEvandro Menezes2017-12-081-0/+31
| | | | | | Differential revision: https://reviews.llvm.org/D40985 llvm-svn: 320195
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-084-46/+21
| | | | | | | | | | | | - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
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