summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Expand)AuthorAgeFilesLines
* [InstCombine] remove checks for IsFreeToInvert()Sanjay Patel2018-09-131-3/+1
* [InstCombine] reorder folds to reduce chance of infinite loopsSanjay Patel2018-09-131-22/+20
* [ARM] Allow truncs as sources in ARM CGPSam Parker2018-09-131-19/+23
* [ARM] Fix FixConst for ARMCodeGenPrepareSam Parker2018-09-131-20/+3
* [MC/Dwarf] Unclamp DWARF linetables format on Darwin.Jonas Devlieghere2018-09-131-7/+1
* AMDGPU: Fix not preserving alignent in call setupsMatt Arsenault2018-09-131-1/+7
* DAG: Fix expansion of unaligned FP loads and storesMatt Arsenault2018-09-131-4/+6
* Fix unused variable warning. NFCI.Simon Pilgrim2018-09-131-1/+1
* ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4.Tim Northover2018-09-135-1/+24
* [XRay] Bug fixes for FDR custom event and arg-loggingDean Michael Berris2018-09-132-21/+7
* [AMDGPU] Load divergence predicate refactoringAlexander Timofeev2018-09-132-8/+26
* [mips] Enable the mnemonic spell correctorSimon Atanasyan2018-09-131-1/+7
* [AMDGPU] Preliminary patch for divergence driven instruction selection. L...Alexander Timofeev2018-09-131-0/+1
* [X86] Type legalize v2i32 div/rem by scalarizing rather than promotingCraig Topper2018-09-131-0/+17
* ARM: correct the relocation type for `bl` on WoASaleem Abdulrasool2018-09-131-1/+1
* Remove isAsCheapAsAMove from v128.constThomas Lively2018-09-131-1/+1
* Remove isAsCheapAsAMove from mem opsThomas Lively2018-09-131-2/+2
* [WebAssembly] Add missing SIMD instruction attributesThomas Lively2018-09-131-2/+3
* DebugInfo/PDB: Remove unused memberDavid Blaikie2018-09-131-2/+2
* dwarfdump: Improve performance on large DWP filesDavid Blaikie2018-09-121-8/+21
* [DAGCombiner] improve formatting for select+setcc code; NFCSanjay Patel2018-09-121-17/+15
* fix 80-column violation with clang-formatAdrian Prantl2018-09-121-7/+4
* [PDB] Remove all clone() methods.Zachary Turner2018-09-1218-98/+0
* [Hexagon] Use shuffles when lowering "gather" shufflevectorsKrzysztof Parzyszek2018-09-121-0/+70
* [Hexagon] Improve the selection algorithm in scalarizeShuffleKrzysztof Parzyszek2018-09-121-22/+89
* [Support] sys::fs::directory_entry includes the file_type.Kristina Brooks2018-09-123-77/+95
* [ORC] Merge ExecutionSessionBase with ExecutionSession by moving a couple ofLang Hames2018-09-122-365/+385
* [ORC] Add a special 'main' JITDylib that is created on ExecutionSessionLang Hames2018-09-121-1/+14
* [WebAssembly] Make tied inline asm operands work againHeejin Ahn2018-09-121-0/+5
* revert r341288 - [Reassociate] swap binop operands to increase factoring pote...Sanjay Patel2018-09-121-64/+0
* [PDB] Emit old fpo data to the PDB file.Zachary Turner2018-09-121-7/+21
* [Hexagon] Use legalized type for extracted elements in scalarizeShuffleKrzysztof Parzyszek2018-09-121-2/+4
* AMDGPU: Print all kernel descriptor directives (including the ones with defau...Konstantin Zhuravlyov2018-09-121-101/+88
* AMDGPU: Re-apply r341982 after fixing the layering issueKonstantin Zhuravlyov2018-09-1212-401/+404
* [InstCombine] Inefficient pattern for high-bits checking (PR38708)Roman Lebedev2018-09-121-0/+38
* [WebAssembly] SIMD comparisonsThomas Lively2018-09-122-1/+55
* [ARM] Tighten f64<->f16 conversion requirementsDiogo N. Sampaio2018-09-121-4/+8
* [X86] Remove isel patterns for ADCX instructionCraig Topper2018-09-121-30/+7
* Reverting r342048, which caused UBSan failures in dsymutil.Wolfgang Pieb2018-09-127-201/+221
* [GVNHoist] computeInsertionPoints() miscalculates IDFAlexandros Lamprineas2018-09-121-4/+2
* [AArch64] Implement aarch64_vector_pcs codegen support.Sander de Smalen2018-09-123-41/+92
* [DWARF] Refactoring range list dumping to fold DWARF v4 functionality into v5...Wolfgang Pieb2018-09-127-221/+201
* [CGP] Ensure splitgep gives deterministic outputDavid Green2018-09-121-1/+1
* [ARM] Follow-up to rL342033Sam Parker2018-09-121-1/+1
* [SimplifyCFG] Put an alignment on generated switch tablesDavid Green2018-09-121-0/+3
* [AArch64] NFC: Refactoring to prepare for vector PCS.Sander de Smalen2018-09-121-39/+74
* [ARM] Exchange MAC operands in ARMParallelDSPSam Parker2018-09-121-115/+154
* [ARM] Allow bitcasts in ARMCodeGenPrepareSam Parker2018-09-121-5/+4
* [AArch64] Add parsing of aarch64_vector_pcs attribute.Sander de Smalen2018-09-126-0/+13
* [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC)Florian Hahn2018-09-122-694/+338
OpenPOWER on IntegriCloud