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* [RISCV] Fix wrong CFI directivesLuís Marques2019-11-141-55/+0
| | | | | | | | | | | | | Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723
* [ExpandReductions] Don't push all intrinsics to the worklist. Just push ↵Craig Topper2019-11-141-10/+29
| | | | | | | | | | | | | | | | | reductions. We were previously pushing all intrinsics used in a function to the worklist. This is wasteful for memory in a function with a lot of intrinsics. We also ask TTI if we should expand every intrinsic, but we only have expansion support for the reduction intrinsics. This just wastes time for the non-reduction intrinsics. This patch only pushes reduction intrinsics into the worklist and skips other intrinsics. Differential Revision: https://reviews.llvm.org/D69470
* Replace wrongly deleted header banner, fix formattingReid Kleckner2019-11-142-11/+20
| | | | | | | | I reviewed the diff hunks of 05da2fe52162c80dfa that don't contain '#include' lines, and found two unintended changes. I deleted a header banner inadvertently while inserting a header, and changed the indentation of a constructor in an odd way. Add back the banner, and reformat the constructor.
* [InstCombine] remove duplicate code for simplifying a shuffle; NFCISanjay Patel2019-11-141-7/+0
| | | | | The transform is already handled by InstSimplify or earlier in InstCombine, so trying to do it again is not necessary.
* Improve VFS compatibility on WindowsAdrian McCarthy2019-11-141-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Keys in a virtual file system can be in Posix or Windows form or even a combination of the two. Many VFS tests (and a few Clang tests) were XFAILed on Windows because of false negatives when comparing paths. First, we default CaseSenstive to false on Windows. This allows drive letters like "D:" to match "d:". Windows filesystems are, by default, case insensitive, so this makes sense even beyond the drive letter. Second, we allow slashes to match backslashes when they're used as the root component of a path. Both of these changes are limited to RedirectingFileSystems, so there's little chance of affecting other path handling. These changes allow eleven of the VFS tests to pass on Windows as well as three other Clang tests, so they have re-enabled. This solves the majority of PR43272. Additional VFS test failures will be fixed in separate patches. Differential Revision: https://reviews.llvm.org/D69958
* Revert "[ThinLTO] Add correctness check for RO/WO variable import"Benjamin Kramer2019-11-145-65/+38
| | | | | This reverts commit a2292cc537b561416c21e8d4017715d652c144cc. Breaks clang selfhost w/ThinLTO.
* On FreeBSD use AT_EXECPATH from ELF auxiliary vectors for getExecutablePathEd Maste2019-11-141-5/+41
| | | | | | | | | | /proc/curproc/file and the KERN_PROC_PATHNAME sysctl may not return the desired path if there are multiple hardlinks to the file, or if the path has expired from the namecache. Reviewed By: theraven Differential Revision: https://reviews.llvm.org/D70198
* ARM: allow rewriting frame indexes for all prefetch variants.Tim Northover2019-11-141-0/+14
| | | | | For some reason we could handle PLD but not PLDW or PLI, but all of them can potentially refer to the stack region (if weirdly for PLI).
* GCOVProfiling - fix uninitialized variable warnings + make getFuncChecksum() ↵Simon Pilgrim2019-11-141-3/+3
| | | | const. NFCI.
* WholeProgramDevirt - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-141-2/+2
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* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-141-1/+1
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* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-141-2/+2
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* SROA - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-141-5/+5
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* Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-142-6/+5
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* Hexagon - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-144-6/+6
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* MSP430 - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-143-21/+18
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* [AArch64][SVE] Implement floating-point comparison & reduction intrinsicsKerry McLaughlin2019-11-142-16/+28
| | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - fadda & faddv - fminv, fmaxv, fminnmv & fmaxnmv - facge & facgt - fcmp[eq|ge|gt|ne|uo] Reviewers: sdesmalen, huntergr, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69858
* [LV] PreferPredicateOverEpilog respecting predicate loop hintSjoerd Meijer2019-11-142-3/+5
| | | | | | | | | | | The vectoriser queries TTI->preferPredicateOverEpilogue to determine if tail-folding is preferred for a loop, but it was not respecting loop hint 'predicate' that can disable this, which has now been added. This showed that we were incorrectly initialising loop hint 'vectorize.predicate.enable' with 0 (i.e. FK_Disabled) but this should have been FK_Undefined, which has been fixed. Differential Revision: https://reviews.llvm.org/D70125
* [DAGCombiner] Drop redundant DAG method param. NFCPaweł Bylica2019-11-141-4/+3
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* [DAGCombiner] Use TLI field already available. NFCPaweł Bylica2019-11-141-3/+0
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* [mips][NFC] Remove old FIXME commentMiloš Stojanović2019-11-141-1/+0
| | | | | | This was fixed in rL229595 but this comment was missed. Differential Revision: https://reviews.llvm.org/D70231
* [AArch64][SVE] Implement remaining floating-point arithmetic intrinsicsKerry McLaughlin2019-11-142-19/+40
| | | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - fabs & fneg - fexpa - frint[a|i|m|n|p|x|z] - frecpe, frecps & frecpx - fsqrt, frsqrte & frsqrts Reviewers: huntergr, sdesmalen, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69800
* [AArch64][SVE] Implement additional floating-point arithmetic intrinsicsKerry McLaughlin2019-11-143-38/+104
| | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - ftssel - fcadd, fcmla - fmla, fmls, fnmla, fnmls - fmad, fmsb, fnmad, fnmsb Reviewers: sdesmalen, huntergr, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69707
* Revert "[InstCombine] Fold PHIs with equal incoming pointers"Daniil Suchkov2019-11-142-70/+0
| | | | | This reverts commit a2f6ae9abffcba260c22bb235879f0576bf3b783. It is reverted due to clang-cmake-armv7-selfhost buildbot failure.
* [InstCombine] Fold PHIs with equal incoming pointersDaniil Suchkov2019-11-142-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | This is a resubmission of bbb29738b58aaf6f6518269abdcf8f64131665a9 that was reverted due to clang tests failures. It includes the fix and additional IR tests for the missed case. Summary: In case when all incoming values of a PHI are equal pointers, this transformation inserts a definition of such a pointer right after definition of the base pointer and replaces with this value both PHI and all it's incoming pointers. Primary goal of this transformation is canonicalization of this pattern in order to enable optimizations that can't handle PHIs. Non-inbounds pointers aren't currently supported. Reviewers: spatel, RKSimon, lebedev.ri, apilipenko Reviewed By: apilipenko Tags: #llvm Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D68128
* [AArch64][DebugInfo] Fix incorrect call site param value produced by MOVZXiDjordje Todorovic2019-11-141-1/+1
| | | | | | This resolves the problem with the truncation of the immediate operand. Differential Revision: https://reviews.llvm.org/D70168
* [NFC] Fix typo in ARMBaseRegisterInfoAnna Welker2019-11-141-1/+1
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* [ThinLTO] Add correctness check for RO/WO variable importevgeny2019-11-145-38/+65
| | | | | | | | | | | This patch adds an assertion check for exported read/write-only variables to be also in import list for module. If they aren't we may face linker errors, because read/write-only variables are internalized in their source modules. The patch also changes export lists to store ValueInfo instead of GUID for performance considerations. Differential revision: https://reviews.llvm.org/D70128
* DWARFDebugLoclists: stricter base address handlingPavel Labath2019-11-143-17/+14
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This removes the use of zero as a base address in section-based dumping. Although this will often be true for (unlinked) object files with a single compile unit, it is not true in general. This means that section-based dumping will not be able to resolve entries referencing the base address (DW_LLE_offset_pair) -- it wasn't able to do that correctly before either, but now it will be more explicit about it. One exception to that is if the location list contains an explicit DW_LLE_base_address entry -- in this case the dumper will pick it up, and resolve subsequent entries normally. The patch also removes the fallback to zero in the "inline" dumping in case the compile unit does not contain a base address. Reviewers: dblaikie, probinson, JDevlieghere, aprantl, SouraVX Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70115
* Check result of emitStrLen before passing it to CreateGEPDimitry Andric2019-11-141-2/+2
| | | | | | | | | | | | | | | | | | Summary: This fixes PR43081, where the transformation of `strchr(p, 0) -> p + strlen(p)` can cause a segfault, if `-fno-builtin-strlen` is used. In that case, `emitStrLen` returns nullptr, which CreateGEP is not designed to handle. Also add the minimized code from the PR as a test case. Reviewers: xbolva00, spatel, jdoerfert, efriedma Reviewed By: efriedma Subscribers: lebedev.ri, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70143
* [mips] Use local variable to escape repetitive calls of `getOpcode`. NFCSimon Atanasyan2019-11-141-13/+10
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* [mips] Use isInt<> call instead of explicit range checking. NFCSimon Atanasyan2019-11-141-2/+1
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* Move CodeGenFileType enum to Support/CodeGen.hReid Kleckner2019-11-134-7/+7
| | | | | | | Avoids the need to include TargetMachine.h from various places just for an enum. Various other enums live here, such as the optimization level, TLS model, etc. Data suggests that this change probably doesn't matter, but it seems nice to have anyway.
* Revert "Forward declare Optional<T> in STLExtras.h"Reid Kleckner2019-11-133-3/+1
| | | | | | This reverts commit a36f316390d4bc1bcb0e9de0f55831385ab24099. I did not intend to push this with the InitializePasses.h change.
* Sink all InitializePasses.h includesReid Kleckner2019-11-13355-129/+555
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file lists every pass in LLVM, and is included by Pass.h, which is very popular. Every time we add, remove, or rename a pass in LLVM, it caused lots of recompilation. I found this fact by looking at this table, which is sorted by the number of times a file was changed over the last 100,000 git commits multiplied by the number of object files that depend on it in the current checkout: recompiles touches affected_files header 342380 95 3604 llvm/include/llvm/ADT/STLExtras.h 314730 234 1345 llvm/include/llvm/InitializePasses.h 307036 118 2602 llvm/include/llvm/ADT/APInt.h 213049 59 3611 llvm/include/llvm/Support/MathExtras.h 170422 47 3626 llvm/include/llvm/Support/Compiler.h 162225 45 3605 llvm/include/llvm/ADT/Optional.h 158319 63 2513 llvm/include/llvm/ADT/Triple.h 140322 39 3598 llvm/include/llvm/ADT/StringRef.h 137647 59 2333 llvm/include/llvm/Support/Error.h 131619 73 1803 llvm/include/llvm/Support/FileSystem.h Before this change, touching InitializePasses.h would cause 1345 files to recompile. After this change, touching it only causes 550 compiles in an incremental rebuild. Reviewers: bkramer, asbirlea, bollu, jdoerfert Differential Revision: https://reviews.llvm.org/D70211
* Forward declare Optional<T> in STLExtras.hReid Kleckner2019-11-133-1/+3
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* Sink MachineFunction private method out of lineReid Kleckner2019-11-131-0/+9
| | | | | | | This method is private and only called from this file and doesn't need to be inline. Saves a TargetMachine.h include in MachineFunction.h, a popular header. The include was introduced in 98603a8153086 despite the forward decl of LLVMTargetMachine.
* [X86] Don't treat mxcsr as a register name when parsing MS inline assembly.Craig Topper2019-11-131-2/+3
| | | | | No instruction takes mxcsr as a an operand so we should always treat it as an identifier name.
* [X86] Don't set the operation action for i16 SINT_TO_FP to Promote just ↵Craig Topper2019-11-131-3/+9
| | | | | | | because SSE1 is enabled. Instead do custom promotion in the handler so that we can still allow i16 to be used with fp80. And f64 without sse2.
* [X86] Fix typo in comment. NFCCraig Topper2019-11-131-1/+1
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* [X86] Move all the FP_TO_XINT/XINT_TO_FP setOperationActions into the same ↵Craig Topper2019-11-131-41/+28
| | | | | | | | | !useSoftFloat block. Qualify all of the Promote actions for these with !useSoftFloat too. NFCI The Promote action doesn't apply until LegalizeDAG. By the time we get there, we would have already softened all the FP operations if useSoftFloat was true. So there wouldn't be any operation left to Promote.
* [PGO][PGSO] Temporarily disable the large working set size behavior.Hiroshi Yamauchi2019-11-131-0/+5
| | | | | | | | | | | | | | Summary: This temporarily disables the large working set size behavior in profile guided size optimization due to internal benchmark regressions. Reviewers: davidxl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70207
* [SLP] fix miscompile on min/max reductions with extra uses (PR43948)Sanjay Patel2019-11-131-1/+14
| | | | | | | | | | | | | | | | | The bug manifests as replacing a reduction operand with an undef value. The problem appears to be limited to cases where a min/max reduction has extra uses of the compare operand to the select. In the general case, we are tracking "ExternallyUsedValues" and an "IgnoreList" of the reduction operations, but those may not apply to the final compare+select in a min/max reduction. For that, we use replaceAllUsesWith (RAUW) to ensure that the new vectorized reduction values are transferred to all subsequent users. Differential Revision: https://reviews.llvm.org/D70148
* [TargetLowering] Increase the storage size of NumRegistersForVT to allow the ↵Craig Topper2019-11-131-1/+4
| | | | | | | | | | type break down for v256i1 and other types to be stored correctly v256i1 on X86 without avx512 breaks down to 256 i8 values when passed between basic blocks. But the NumRegistersForVT was sized at a byte for each VT. This results in 256 being stored as 0. This patch enlarges the type to 16 bits and adds an assert to ensure that no information is lost when the entry is stored. Differential Revision: https://reviews.llvm.org/D70138
* [mips] Reduce number of nested `if` statements. NFCSimon Atanasyan2019-11-131-8/+5
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* [mips] Add tests to check `jal sym+offset`. NFCSimon Atanasyan2019-11-131-2/+0
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* [LiveInterval] Allow updating subranges with slightly out-dated IRQuentin Colombet2019-11-134-10/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During register coalescing, we update the live-intervals on-the-fly. To do that we are in this strange mode where the live-intervals can be slightly out-of-sync (more precisely they are forward looking) compared to what the IR actually represents. This happens because the register coalescer only updates the IR when it is done with updating the live-intervals and it has to do it this way because updating the IR on-the-fly would actually clobber some information on how the live-ranges that are being updated look like. This is problematic for updates that rely on the IR to accurately represents the state of the live-ranges. Right now, we have only one of those: stripValuesNotDefiningMask. To reconcile this need of out-of-sync IR, this patch introduces a new argument to LiveInterval::refineSubRanges that allows the code doing the live range updates to reason about how the code should look like after the coalescer will have rewritten the registers. Essentially this captures how a subregister index with be offseted to match its position in a new register class. E.g., let say we want to merge: V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32> We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32> overlap, i.e., by choosing a class where we can find "offset + 1 == 3". Put differently we align V2's sub3 with V1's sub1: V2: sub0 sub1 sub2 sub3 V1: <offset> sub0 sub1 This offset will look like a composed subregidx in the the class: V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> => V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> Now if we didn't rewrite the uses and def of V1, all the checks for V1 need to account for this offset to match what the live intervals intend to capture. Prior to this patch, we would fail to recognize the uses and def of V1 and would end up with machine verifier errors: No live segment at def. This could lead to miscompile as we would drop some live-ranges and thus, miss some interferences. For this problem to trigger, we need to reach stripValuesNotDefiningMask while having a mismatch between the IR and the live-ranges (i.e., we have to apply a subreg offset to the IR.) This requires the following three conditions: 1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1> 2. An update with Tuple registers with a possibility to coalesce the subreg index: e.g., v1.dsub_1 == v2.dsub_3 3. Subreg liveness enabled. looking at the IR to decide what is alive and what is not, i.e., calling stripValuesNotDefiningMask. coalescer maintains for the live-ranges information. None of the targets that currently use subreg liveness (i.e., the targets that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and and #2, so this patch also artificial enables subreg liveness for ARM, so that a nice test case can be attached.
* [AArch64][v8.3a] Add missing imp-defs on RETA*.Ahmed Bougacha2019-11-131-0/+1
| | | | | | | | | | | | | RETA always implicitly uses LR, unlike RET which merely has an alias that defaults it to LR. Additionally, RETA implicitly uses SP as well, which it uses as a discriminator to authenticate LR. This isn't usually noticeable, because RET_ReallyLR is used in most of the backend. However, the post-RA scheduler, if enabled, will cause miscompiles if the imp-uses are missing. While there, fix a typo in the lone affected testcase.
* [AArch64][v8.3a] Add LDRA '[xN]!' alias.Ahmed Bougacha2019-11-131-0/+3
| | | | | | The instruction definition has been retroactively expanded to allow for an alias for '[xN, 0]!' as '[xN]!'. That wouldn't make sense on LDR, but does for LDRA.
* Fix typo in DwarfDebug [NFC]David Stenberg2019-11-131-1/+1
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