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| author | Tim Northover <t.p.northover@gmail.com> | 2019-11-14 13:26:53 +0000 |
|---|---|---|
| committer | Tim Northover <t.p.northover@gmail.com> | 2019-11-14 14:26:28 +0000 |
| commit | 232cdb3d3018b4bda60a2a62c3b071ad3af8bd35 (patch) | |
| tree | dff9da9e95044cac080da23b49810eb11722aad9 /llvm/lib | |
| parent | edfc94e296f1faa6414ac91b86856b107a0568ac (diff) | |
| download | bcm5719-llvm-232cdb3d3018b4bda60a2a62c3b071ad3af8bd35.tar.gz bcm5719-llvm-232cdb3d3018b4bda60a2a62c3b071ad3af8bd35.zip | |
ARM: allow rewriting frame indexes for all prefetch variants.
For some reason we could handle PLD but not PLDW or PLI, but all of them can
potentially refer to the stack region (if weirdly for PLI).
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index c061db1cc7f..4a459d2c2fb 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -375,6 +375,8 @@ negativeOffsetOpcode(unsigned opcode) case ARM::t2STRBi12: return ARM::t2STRBi8; case ARM::t2STRHi12: return ARM::t2STRHi8; case ARM::t2PLDi12: return ARM::t2PLDi8; + case ARM::t2PLDWi12: return ARM::t2PLDWi8; + case ARM::t2PLIi12: return ARM::t2PLIi8; case ARM::t2LDRi8: case ARM::t2LDRHi8: @@ -385,6 +387,8 @@ negativeOffsetOpcode(unsigned opcode) case ARM::t2STRBi8: case ARM::t2STRHi8: case ARM::t2PLDi8: + case ARM::t2PLDWi8: + case ARM::t2PLIi8: return opcode; default: @@ -405,6 +409,8 @@ positiveOffsetOpcode(unsigned opcode) case ARM::t2STRBi8: return ARM::t2STRBi12; case ARM::t2STRHi8: return ARM::t2STRHi12; case ARM::t2PLDi8: return ARM::t2PLDi12; + case ARM::t2PLDWi8: return ARM::t2PLDWi12; + case ARM::t2PLIi8: return ARM::t2PLIi12; case ARM::t2LDRi12: case ARM::t2LDRHi12: @@ -415,6 +421,8 @@ positiveOffsetOpcode(unsigned opcode) case ARM::t2STRBi12: case ARM::t2STRHi12: case ARM::t2PLDi12: + case ARM::t2PLDWi12: + case ARM::t2PLIi12: return opcode; default: @@ -435,6 +443,8 @@ immediateOffsetOpcode(unsigned opcode) case ARM::t2STRBs: return ARM::t2STRBi12; case ARM::t2STRHs: return ARM::t2STRHi12; case ARM::t2PLDs: return ARM::t2PLDi12; + case ARM::t2PLDWs: return ARM::t2PLDWi12; + case ARM::t2PLIs: return ARM::t2PLIi12; case ARM::t2LDRi12: case ARM::t2LDRHi12: @@ -445,6 +455,8 @@ immediateOffsetOpcode(unsigned opcode) case ARM::t2STRBi12: case ARM::t2STRHi12: case ARM::t2PLDi12: + case ARM::t2PLDWi12: + case ARM::t2PLIi12: case ARM::t2LDRi8: case ARM::t2LDRHi8: case ARM::t2LDRBi8: @@ -454,6 +466,8 @@ immediateOffsetOpcode(unsigned opcode) case ARM::t2STRBi8: case ARM::t2STRHi8: case ARM::t2PLDi8: + case ARM::t2PLDWi8: + case ARM::t2PLIi8: return opcode; default: |
