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* Follow-up for r217020: actually commit the fix for PR20800,Alexander Potapenko2014-09-031-3/+22
| | | | | | revert the accidentally committed changes to LLVMSymbolize.cpp llvm-svn: 217021
* Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-09-031-79/+128
| | | | | | | | | | | | | | | | for MADD, SUB, and OR."" This reapplies r216805 with a fix to a copy-past error, which resulted in an incorrect register class. Original commit message: Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 217019
* [MCJIT] Make llvm-rtdyld process eh_frame sections in -verify mode (accidentallyLang Hames2014-09-031-1/+0
| | | | | | | | left out of r217010). Also remove a crufty debugging output statement that was accidentally left in. llvm-svn: 217011
* [MCJIT] Add a 'section_addr' builtin function to RuntimeDyldChecker.Lang Hames2014-09-033-25/+141
| | | | | | | | | | The syntax of the new builtin is 'section_addr(<filename>, <section-name>)' (similar to the stub_addr builtin, but without a symbol name). It returns the base address of the given section in the given object file. This builtin makes it possible to refer to the contents of sections that cannot contain symbols, e.g. sections added by the linker itself, like __eh_frame. llvm-svn: 217010
* [FastISel][AArch64] Add target-dependent instruction selection for Add/Sub.Juergen Ributzka2014-09-031-187/+164
| | | | | | | | | | | There is already target-dependent instruction selection support for Adds/Subs to support compares and the intrinsics with overflow check. This takes advantage of the existing infrastructure to also support Add/Sub, which allows the folding of immediates, sign-/zero-extends, and shifts. This fixes rdar://problem/18207316. llvm-svn: 217007
* Change name of copyFlags() to copyIRFlags(). Add convenience method for ↵Sanjay Patel2014-09-032-2/+19
| | | | | | | | | | logical 'and' of all flags. NFC. Adding 'IR' to the names in an attempt to be less ambiguous about the flags we're dealing with here. The 'and' method is needed by the SLPVectorizer (PR20802) and possibly other passes. llvm-svn: 217004
* [CFLAA] Remove one final initializer listHal Finkel2014-09-031-1/+5
| | | | | | Maybe MSVC will be happy now... llvm-svn: 217000
* [CFLAA] And even more MSVC fixesHal Finkel2014-09-022-3/+6
| | | | | | Remove a couple more initializer lists and constexpr dependencies. llvm-svn: 216998
* Cleaning up remaining static initializers in Signals.incChris Bieneman2014-09-021-24/+31
| | | | llvm-svn: 216996
* [CFLAA] More cleanup for MSVCHal Finkel2014-09-022-11/+14
| | | | | | Remove more initializer lists, etc. llvm-svn: 216994
* [CFLAA] No initializer lists for MSVCHal Finkel2014-09-022-28/+30
| | | | | | MSVC 2012 does not understand initializer lists; remove them. llvm-svn: 216991
* Only emit movw on ARMv6T2+Renato Golin2014-09-021-1/+2
| | | | | | | | Fix PR18364. Patch by Dimitry Andric. llvm-svn: 216989
* unique_ptrify passing the TargetMachine to ExecutionEngine::MCJITCtorDavid Blaikie2014-09-023-16/+12
| | | | llvm-svn: 216988
* [CFLAA] Remove tautological comparisonHal Finkel2014-09-021-1/+1
| | | | | | | | Fixes this (the warning is right, the unsigned value is not negative): lib/Analysis/StratifiedSets.h:689:53: warning: comparison of unsigned expression >= 0 is always true [-Wtautological-compare] bool inbounds(StratifiedIndex N) const { return N >= 0 && N < Links.size(); } llvm-svn: 216987
* [FastISel][AArch64] Use the target-dependent selection code for shifts first.Juergen Ributzka2014-09-021-6/+6
| | | | | | | | | | | | This uses the target-dependent selection code for shifts first, which allows us to create better code for shifts with immediates and sign-/zero-extend folding. Vector type are not handled yet and the code falls back to target-independent instruction selection for these cases. This fixes rdar://problem/17907920. llvm-svn: 216985
* [FastISel][AArch64] Use a new helper function to determine if a value type ↵Juergen Ributzka2014-09-021-6/+25
| | | | | | | | | | | | is supported. NFCI. FastISel for AArch64 supports more value types than are actually legal. Use a dedicated helper function to reflect this. It is very similar to the isLoadStoreTypeLegal function, with the exception that vector types are not supported yet. llvm-svn: 216984
* Nuke MCAnalysis.Sean Silva2014-09-0212-1668/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code is buggy and barely tested. It is also mostly boilerplate. (This includes MCObjectDisassembler, which is the interface to that functionality) Following an IRC discussion with Jim Grosbach, it seems sensible to just nuke the whole lot of functionality, and dig it up from VCS if necessary (I hope not!). All of this stuff appears to have been added in a huge patch dump (look at the timeframe surrounding e.g. r182628) where almost every patch seemed to be untested and not reviewed before being committed. Post-review responses to the patches were never addressed. I don't think any of it would have passed pre-commit review. I doubt anyone is depending on this, since this code appears to be extremely buggy. In limited testing that Michael Spencer and I did, we couldn't find a single real-world object file that wouldn't crash the CFG reconstruction stuff. The symbolizer stuff has O(n^2) behavior and so is not much use to anyone anyway. It seemed simpler to remove them as a whole. Most of this code is boilerplate, which is the only way it was able to scrape by 60% coverage. HEADSUP: Modules folks, some files I nuked were referenced from include/llvm/module.modulemap; I just deleted the references. Hopefully that is the right fix (one was a FIXME though!). llvm-svn: 216983
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-0288-9552/+61
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* [CFLAA] LLVM_CONSTEXPR -> constHal Finkel2014-09-021-1/+1
| | | | | | | The number is just a constant, and this should make MSVC happy (or at least happier). llvm-svn: 216981
* [X86] Allow atomic operations using immediates to avoid using a registerRobin Morisset2014-09-023-38/+167
| | | | | | | | | | | | | | | | The only valid lowering of atomic stores in the X86 backend was mov from register to memory. As a result, storing an immediate required a useless copy of the immediate in a register. Now these can be compiled as a simple mov. Similarily, adding/and-ing/or-ing/xor-ing an immediate to an atomic location (but through an atomic_store/atomic_load, not a fetch_whatever intrinsic) can now make use of an 'add $imm, x(%rip)' instead of using a register. And the same applies to inc/dec. This second point matches the first issue identified in http://llvm.org/bugs/show_bug.cgi?id=17281 llvm-svn: 216980
* [CFLAA] constexpr -> LLVM_CONSTEXPRHal Finkel2014-09-022-13/+15
| | | | | | Attempt to fix the MSVC build by not using constexpr. llvm-svn: 216979
* Add pass-manager flags to use CFL AAHal Finkel2014-09-022-0/+11
| | | | | | | Add -use-cfl-aa (and -use-cfl-aa-in-codegen) to add CFL AA in the default pass managers (for easy testing). llvm-svn: 216978
* [asan] Assign a low branch weight to ASan's slow path, patch by Jonas ↵Kostya Serebryany2014-09-022-2/+5
| | | | | | Wagner. This speeds up asan (at least on SPEC) by 1%-5% or more. Also fix lint in dfsan. llvm-svn: 216972
* Add a CFL Alias Analysis implementationHal Finkel2014-09-024-0/+1674
| | | | | | | | | | | | | | | | This provides an implementation of CFL alias analysis (including some supporting data structures). Currently, we don't have any extremely fancy features, sans some interprocedural analysis (i.e. no field sensitivity, etc.), and we do best sitting behind BasicAA + TBAA. In such a configuration, we take ~0.6-0.8% of total compile time, and give ~7-8% NoAlias responses to queries TBAA and BasicAA couldn't answer when bootstrapping LLVM. In testing this on other projects, we've seen up to 10.5% of queries dropped by BasicAA+TBAA answered with NoAlias by this algorithm. Patch by George Burgess IV (with minor modifications by me -- mostly adapting some BasicAA tests), thanks! llvm-svn: 216970
* [FastISel][AArch64] Move over to target-dependent instruction selection only.Juergen Ributzka2014-09-021-41/+133
| | | | | | | | | | | This change moves FastISel for AArch64 to target-dependent instruction selection only. This change replicates the existing target-independent behavior, therefore there are no changes to the unit tests or new tests. Future changes will take advantage of this change and update functionality and unit tests. llvm-svn: 216955
* [FastISel] Provide the option to skip target-independent instruction ↵Juergen Ributzka2014-09-021-18/+24
| | | | | | | | | | | | | selection. NFC. This allows the target to disable target-independent instruction selection and jump directly into the target-dependent instruction selection code. This can be beneficial for targets, such as AArch64, which could emit much better code, but never got a chance to do so, because the target-independent instruction selector was able to find an instruction sequence. llvm-svn: 216947
* Generate extract for in-tree uses if the use is scalar operand in vectorized ↵Yi Jiang2014-09-021-18/+69
| | | | | | instruction. radar://18144665 llvm-svn: 216946
* Refactor LowerFABS and LowerFNEG into one function (x86) (NFC)Sanjay Patel2014-09-021-42/+31
| | | | | | | | | We duplicate ~30 lines of code to lower FABS and FNEG for x86, so this patch combines them into one function. No functional change intended, so no additional test cases. Test-suite behavior is unchanged. Differential Revision: http://reviews.llvm.org/D5064 llvm-svn: 216942
* Fix MemoryDependenceAnalysis in cases where QueryInstr is a CmpXchg or a ↵Robin Morisset2014-09-021-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AtomicRMW Summary: MemoryDependenceAnalysis is currently cautious when the QueryInstr is an atomic load or store, but I forgot to check for atomic cmpxchg/atomicrmw. This patch is a way of fixing that, and making it less brittle (i.e. no risk that I forget another possible kind of atomic, even if the IR ends up changing in the future), by adding a fallback checking mayReadOrWriteFromMemory. Thanks to Philip Reames for finding this bug and suggesting this solution in http://reviews.llvm.org/D4845 Sadly, I don't see how to add a test for this, since the passes depending on MemoryDependenceAnalysis won't trigger for an atomic rmw anyway. Does anyone see a way for testing it? Test Plan: none possible at first sight Reviewers: jfb, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5019 llvm-svn: 216940
* Fix a logic bug when copying fast-math flags.Sanjay Patel2014-09-022-2/+7
| | | | | | | | | | | | | "Setting" does not equal "copying". This bug has sat dormant for 2 reasons: 1. The unit test was not adequate. 2. Every current user of the "copyFastMathFlags" API is operating on a new instruction. (ie, all existing fast-math flags are off). If you copy flags to an existing instruction that has some flags on already, you will not necessarily turn them off as expected. I uncovered this bug while trying to implement a fix for PR20802. llvm-svn: 216939
* Fix interference caused by fmul 2, x -> fadd x, xMatt Arsenault2014-09-021-8/+21
| | | | | | | | If an fmul was introduced by lowering, it wouldn't be folded into a multiply by a constant since the earlier combine would have replaced the fmul with the fadd. llvm-svn: 216932
* Code review tweaksNick Kledzik2014-09-021-9/+9
| | | | llvm-svn: 216931
* CodeGen: Handle va_start in the entry blockReid Kleckner2014-09-022-26/+18
| | | | | | | | | Also fix a small copy-paste bug in X86ISelLowering where Chain should have been used in place of DAG.getEntryToken(). Fixes PR20828. llvm-svn: 216929
* Fix comment and unnecessary check for FP build_vectors.Matt Arsenault2014-09-021-5/+1
| | | | | | | This was copy-paste from the integer version, but FP build_vectors don't truncate. llvm-svn: 216928
* unique_ptrify LTOCodeGenerator::NativeObjectFileDavid Blaikie2014-09-021-7/+2
| | | | llvm-svn: 216927
* unique_ptrify the result of SpecialCaseList::createDavid Blaikie2014-09-022-8/+9
| | | | llvm-svn: 216925
* unique_ptrify FileOutputBuffer::FileOutputBufferDavid Blaikie2014-09-021-10/+7
| | | | llvm-svn: 216921
* Fix left shifts of negative values in MipsDisassembler.Alexey Samsonov2014-09-021-15/+15
| | | | | | This bug was reported by UBSan. llvm-svn: 216920
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-0217-37/+35
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
* unique_ptrify PBQPBuilder::buildDavid Blaikie2014-09-021-13/+13
| | | | llvm-svn: 216918
* Fix signed integer overflow in PPCInstPrinter.Alexey Samsonov2014-09-021-1/+1
| | | | | | This bug was reported by UBSan. llvm-svn: 216917
* Fix left shifts by too large exponents in MCParserAlexey Samsonov2014-09-021-7/+8
| | | | | | | | (which happened only on error recovery path). This bug was reported by UBSan. llvm-svn: 216915
* Revert: [APFloat] Fixed a bug in method 'fusedMultiplyAdd'.Andrea Di Biagio2014-09-021-1/+1
| | | | | | | This reverts revision 216913; the new test added at revision 216913 caused regression failures on a couple of buildbots. llvm-svn: 216914
* [APFloat] Fixed a bug in method 'fusedMultiplyAdd'.Andrea Di Biagio2014-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | When folding a fused multiply-add builtin call, make sure that we propagate the correct result in the case where the addend is zero, and the two other operands are finite non-zero. Example: define double @test() { %1 = call double @llvm.fma.f64(double 7.0, double 8.0, double 0.0) ret double %1 } Before this patch, the instruction simplifier wrongly folded the builtin call in function @test to constant 'double 7.0'. With this patch, method 'fusedMultiplyAdd' correctly evaluates the multiply and propagates the expected result (i.e. 56.0). Added test fold-builtin-fma.ll with the reproducible from PR20832 plus extra test cases to verify the behavior of method 'fusedMultiplyAdd' in the presence of NaN/Inf operands. This fixes PR20832. Differential Revision: http://reviews.llvm.org/D5152 llvm-svn: 216913
* Add missing override on ARMAsmBackend's dtor.JF Bastien2014-09-021-2/+1
| | | | | | | | | | Test Plan: ninja check && ninja clang-test Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D5075 llvm-svn: 216912
* LICM: Don't crash when an instruction is used by an unreachable BBDavid Majnemer2014-09-021-1/+6
| | | | | | | | | | | | | | | | | | | Summary: BBs might contain non-LCSSA'd values after the LCSSA pass is run if they are unreachable from the entry block. Normally, the users of the instruction would be PHIs but the unreachable BBs have normal users; rewrite their uses to be undef values. An alternative fix could involve fixing this at LCSSA but that would require this invariant to hold after subsequent transforms. If a BB created an unreachable block, they would be in violation of this. This fixes PR19798. Differential Revision: http://reviews.llvm.org/D5146 llvm-svn: 216911
* Fix left shifts of negative integers in AArch64 InstPrinter/DisassemblerAlexey Samsonov2014-09-022-5/+5
| | | | | | | | | | | | | | | | | | | Summary: Left shift of negative integer is an undefined behavior, and is reported by UBSan. It's ok for imm values to be negative, so we can just replace left shifts with multiplications. Test Plan: check-llvm test suite Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5132 llvm-svn: 216910
* Enable splitting indexing from loads with TargetConstantsHal Finkel2014-09-021-8/+21
| | | | | | | | | | | | When I recommitted r208640 (in r216898) I added an exclusion for TargetConstant offsets, as there is no guarantee that a backend can handle them on generic ADDs (even if it generates them during address-mode matching) -- and, specifically, applying this transformation directly with TargetConstants caused a self-hosting failure on PPC64. Ignoring all TargetConstants, however, is less than ideal. Instead, for non-opaque constants, we can convert them into regular constants for use with the generated ADD (or SUB). llvm-svn: 216908
* Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly ↵Aaron Ballman2014-09-021-1/+1
| | | | | | converted to 64 bits (was 64-bit shift intended?)). NFC. llvm-svn: 216902
* Merge Extend and Shift into a UBFXDavid Xu2014-09-021-13/+15
| | | | llvm-svn: 216899
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