summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Improve ARM lowering for "icmp <2 x i64> eq".Eli Friedman2016-10-181-6/+21
| | | | | | | | | The custom lowering is pretty straightforward: basically, just AND together the two halves of a <4 x i32> compare. Differential Revision: https://reviews.llvm.org/D25713 llvm-svn: 284536
* [GVN] Consistently use division instead of shift. NFCI.Davide Italiano2016-10-181-2/+2
| | | | | | | This is in line with other places of GVN (e.g. load coercion logic). llvm-svn: 284535
* [GVN] Remove dead code. NFC.Davide Italiano2016-10-181-20/+1
| | | | llvm-svn: 284534
* Use profile info to set function section prefix to group hot/cold functions.Dehao Chen2016-10-185-4/+54
| | | | | | | | | | | | | | | | Summary: The original implementation is in r261607, which was reverted in r269726 to accomendate the ProfileSummaryInfo analysis pass. The new implementation: 1. add a new metadata for function section prefix 2. query against ProfileSummaryInfo in CGP to set the correct section prefix for each function 3. output the section prefix set by CGP Reviewers: davidxl, eraman Subscribers: vsk, llvm-commits Differential Revision: https://reviews.llvm.org/D24989 llvm-svn: 284533
* [AArch64] Avoid materializing 0.0 when generating FP SELECTEvandro Menezes2016-10-181-0/+19
| | | | | | | | | | | Transform `a == 0.0 ? 0.0 : x` to `a == 0.0 ? a : x` and `a != 0.0 ? x : 0.0` to `a != 0.0 ? x : a` to avoid materializing 0.0 for FCSEL, since it does not have to be materialized beforehand for FCMP, as it has a form that has 0.0 as an implicit operand. Differential Revision: https://reviews.llvm.org/D24808 llvm-svn: 284531
* One more additional error check for invalid Mach-O files for aKevin Enderby2016-10-181-0/+5
| | | | | | | | | load command that use the MachO:: linkedit_data_command type but is not used in llvm libObject code but used in llvm tool code. This is for the LC_CODE_SIGNATURE load command. llvm-svn: 284529
* GlobalISel: translate the @llvm.objectsize intrinsic.Tim Northover2016-10-181-0/+7
| | | | llvm-svn: 284527
* GlobalISel: select small binary operations on AArch64.Tim Northover2016-10-181-4/+9
| | | | | | | | AArch64 actually supports many 8-bit operations under the definition used by GlobalISel: the designated information-carrying bits of a GPR32 get the right value if you just use the normal 32-bit instruction. llvm-svn: 284526
* GlobalISel: translate memcpy intrinsics.Tim Northover2016-10-181-0/+22
| | | | llvm-svn: 284525
* GlobalISel: support floating-point constants on AArch64.Tim Northover2016-10-181-7/+74
| | | | | | Patch from Ahmed Bougacha. llvm-svn: 284523
* [Hexagon] Handle block live-ins with lane masks in HexagonBlockRangesKrzysztof Parzyszek2016-10-182-11/+28
| | | | llvm-svn: 284522
* Reduce global namespace pollution. NFC.Benjamin Kramer2016-10-187-10/+15
| | | | llvm-svn: 284521
* [esan] Remove global variable.Benjamin Kramer2016-10-181-1/+2
| | | | | | It's not thread safe and completely unnecessary. llvm-svn: 284520
* [InterleavedAccessPass] Remove global variable.Benjamin Kramer2016-10-181-6/+9
| | | | | | | This is a threading hazard and rightfully complained about by tsan. No functionality change. llvm-svn: 284515
* [libFuzzer] detect leaks after every run when executing fixed inputs ↵Kostya Serebryany2016-10-183-2/+6
| | | | | | (./fuzzer -runs=1000000 my-file) llvm-svn: 284514
* revert r284495: [Target] remove TargetRecip classSanjay Patel2016-10-1810-280/+346
| | | | | | There's something wrong with the StringRef usage while parsing the attribute string. llvm-svn: 284513
* [libFuzzer] reshuffle the code for -exit_on_src_pos and -exit_on_itemKostya Serebryany2016-10-182-15/+12
| | | | llvm-svn: 284508
* [asan] Make -asan-experimental-poisoning the only behaviorVitaly Buka2016-10-181-34/+11
| | | | | | | | | | Reviewers: eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25735 llvm-svn: 284505
* Next set of additional error checks for invalid Mach-O files for theKevin Enderby2016-10-181-0/+25
| | | | | | | | | | | load commands that use the MachO::routines_command and and MachO::routines_command_64 types but are not used in llvm libObject code but used in llvm tool code. This includes the LC_ROUTINES and LC_ROUTINES_64 load commands. llvm-svn: 284504
* [SCEV] Make CompareValueComplexity a little bit smarterSanjoy Das2016-10-181-2/+12
| | | | | | | | This helps canonicalization in some cases. Thanks to Pankaj Chawla for the investigation and the test case! llvm-svn: 284501
* [SCEV] Extract out a helper function; NFCSanjoy Das2016-10-181-45/+46
| | | | llvm-svn: 284500
* [Target] remove TargetRecip class; move reciprocal estimate isel ↵Sanjay Patel2016-10-1810-346/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | functionality to TargetLowering This is a follow-up to D24816 - where we changed reciprocal estimates to be function attributes rather than TargetOptions. This patch is intended to be a structural, but not functional change. By moving all of the TargetRecip functionality into TargetLowering, we can remove all of the reciprocal estimate state, shield the callers from the string format implementation, and simplify/localize the logic needed for a target to enable this. If a function has a "reciprocal-estimates" attribute, those settings may override the target's default reciprocal preferences for whatever operation and data type we're trying to optimize. If there's no attribute string or specific setting for the op/type pair, just use the target default settings. As noted earlier, a better solution would be to move the reciprocal estimate settings to IR instructions and SDNodes rather than function attributes, but that's a multi-step job that requires infrastructure improvements. I intend to work on that, but it's not clear how long it will take to get all the pieces in place. Differential Revision: https://reviews.llvm.org/D25440 llvm-svn: 284495
* [DAGCombiner] Add splatted vector support to (udiv x, (shl pow2, y)) -> x ↵Simon Pilgrim2016-10-181-2/+3
| | | | | | >>u (log2(pow2)+y) llvm-svn: 284491
* [X86][AVX512] Add mask/maskz writemask support to constant pool shuffle ↵Simon Pilgrim2016-10-181-24/+36
| | | | | | decode commentx llvm-svn: 284488
* [mips][ias] Handle more complicated expressions for memory operandsSimon Dardis2016-10-181-2/+54
| | | | | | | | | | | | | | | | This patch teaches ias for mips to handle expressions such as (8*4)+(8*31)($sp). Such expression typically occur from the expansion of multiple macro definitions. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24667 llvm-svn: 284485
* [mips] Fix sync instruction definitionSimon Dardis2016-10-182-2/+8
| | | | | | | | | | | | | | | | | | | | | | | The 'sync' instruction for MIPS was defined in MIPS-II as taking no operands. MIPS32 extended the define of 'sync' as taking an optional unsigned 5 bit immediate. This patch correct the definition of sync so that it is accepted with an operand of 0 or no operand for MIPS-II to MIPS-V, and a 5 bit unsigned immediate for MIPS32 and later revisions. Additionally a clear error is given when the MIPS32 version of sync is used when targeting pre MIPS32. This partially resolves PR/30714. Thanks to Daniel Sanders for reporting this issue! Reveiwers: vkalintiris Differential Revision: https://reviews.llvm.org/D25672 llvm-svn: 284483
* DebugInfo: change alignment type from uint64_t to uint32_t to save space.Victor Leschuk2016-10-186-39/+42
| | | | | | | | | In futher patches we shall have alignment field added to DIVariable family and switching from uint64_t to uint32_t will save 4 bytes per variable. Differential Revision: https://reviews.llvm.org/D25620 llvm-svn: 284482
* [mips] Macro expansion for ld, sd for O32Simon Dardis2016-10-182-0/+106
| | | | | | | | | | | | | | | | | | | | | | ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
* [x86][inline-asm][avx512] allow swapping of '{k<num>}' & '{z}' marksMichael Zuckerman2016-10-181-25/+65
| | | | | | | | | | | | | | | | | | | | | | | Committing on behalf of Coby Tayree: After check-all and LGTM Desc: AVX512 allows dest operand to be followed by an op-mask register specifier ('{k<num>}', which in turn may be followed by a merging/zeroing specifier ('{z}') Currently, the following forms are allowed: {k<num>} {k<num>}{z} This patch allows the following forms: {z}{k<num>} and ignores the next form: {z} Justification would be quite simple - GCC Differential Revision: http://reviews.llvm.org/D25013 llvm-svn: 284479
* Strip trailing whitespace (NFCI)Simon Pilgrim2016-10-181-1/+1
| | | | llvm-svn: 284478
* [mips][FastISel] Instantiate the MipsFastISel class only for targets that ↵Vasileios Kalintiris2016-10-182-22/+13
| | | | | | | | | | | | | | | | | | support FastISel. Summary: Instead of instantiating the MipsFastISel class and checking if the target is supported in the overriden methods, we should perform that check before creating the class. This allows us to enable FastISel *only* for targets that truly support it, ie. MIPS32 to MIPS32R5. Reviewers: sdardis Subscribers: ehostunreach, llvm-commits Differential Revision: https://reviews.llvm.org/D24824 llvm-svn: 284475
* [SCEV] More accurate calculation of max backedge count of some less-than loopsJohn Brawn2016-10-181-28/+53
| | | | | | | | | | | | | | | | | | | | | In loops that look something like i = n; do { ... } while(i++ < n+k); where k is a constant, the maximum backedge count is k (in fact the backedge count will be either 0 or k, depending on whether n+k wraps). More generally for LHS < RHS if RHS-(LHS of first comparison) is a constant then the loop will iterate either 0 or that constant number of times. This allows for more loop unrolling with the recent upper bound loop unrolling changes, and I'm working on a patch that will let loop unrolling additionally make use of the loop being executed either 0 or k times (we need to retain the loop comparison only on the first unrolled iteration). Differential Revision: https://reviews.llvm.org/D25607 llvm-svn: 284465
* Revert "Resubmit "Add support for advanced number formatting.""Renato Golin2016-10-182-328/+89
| | | | | | | | | | This reverts commits 284436 and 284437 because they still break AArch64 bots: Value of: format_number(-10, IntegerStyle::Integer, 1) Actual: "-0" Expected: "-10" llvm-svn: 284462
* [ARM] Assign cost of scaling for Cortex-R52Javed Absar2016-10-181-1/+2
| | | | | | | | | | | | This patch assigns cost of the scaling used in addressing for Cortex-R52. On Cortex-R52 a negated register offset takes longer than a non-negated register offset, in a register-offset addressing mode. Differential Revision: http://reviews.llvm.org/D25670 Reviewer: jmolloy llvm-svn: 284460
* [X86][SSE] Add lowering to cvttpd2dq/cvttps2dq for sitofp v2f64/2f32 to 2i32Simon Pilgrim2016-10-186-1/+64
| | | | | | | | | | | | As discussed on PR28461 we currently miss the chance to lower "fptosi <2 x double> %arg to <2 x i32>" to cvttpd2dq due to its use of illegal types. This patch adds support for fptosi to 2i32 from both 2f64 and 2f32. It also recognises that cvttpd2dq zeroes the upper 64-bits of the xmm result (similar to D23797) - we still don't do this for the cvttpd2dq/cvttps2dq intrinsics - this can be done in a future patch. Differential Revision: https://reviews.llvm.org/D23808 llvm-svn: 284459
* [XRay] Support for for tail calls for ARM no-ThumbDean Michael Berris2016-10-184-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds simplified support for tail calls on ARM with XRay instrumentation. Known issue: compiled with generic flags: `-O3 -g -fxray-instrument -Wall -std=c++14 -ffunction-sections -fdata-sections` (this list doesn't include my specific flags like --target=armv7-linux-gnueabihf etc.), the following program #include <cstdio> #include <cassert> #include <xray/xray_interface.h> [[clang::xray_always_instrument]] void __attribute__ ((noinline)) fC() { std::printf("In fC()\n"); } [[clang::xray_always_instrument]] void __attribute__ ((noinline)) fB() { std::printf("In fB()\n"); fC(); } [[clang::xray_always_instrument]] void __attribute__ ((noinline)) fA() { std::printf("In fA()\n"); fB(); } // Avoid infinite recursion in case the logging function is instrumented (so calls logging // function again). [[clang::xray_never_instrument]] void simplyPrint(int32_t functionId, XRayEntryType xret) { printf("XRay: functionId=%d type=%d.\n", int(functionId), int(xret)); } int main(int argc, char* argv[]) { __xray_set_handler(simplyPrint); printf("Patching...\n"); __xray_patch(); fA(); printf("Unpatching...\n"); __xray_unpatch(); fA(); return 0; } gives the following output: Patching... XRay: functionId=3 type=0. In fA() XRay: functionId=3 type=1. XRay: functionId=2 type=0. In fB() XRay: functionId=2 type=1. XRay: functionId=1 type=0. XRay: functionId=1 type=1. In fC() Unpatching... In fA() In fB() In fC() So for function fC() the exit sled seems to be called too much before function exit: before printing In fC(). Debugging shows that the above happens because printf from fC is also called as a tail call. So first the exit sled of fC is executed, and only then printf is jumped into. So it seems we can't do anything about this with the current approach (i.e. within the simplification described in https://reviews.llvm.org/D23988 ). Differential Revision: https://reviews.llvm.org/D25030 llvm-svn: 284456
* Object: Add a missing return in ObjectFile::createObjectFileJustin Bogner2016-10-181-2/+2
| | | | | | | | When Error was threaded through these APIs back in r265606 the "return" was missed here, which triggers a warning if/when I add LLVM_NODISCARD to the Error type. llvm-svn: 284454
* [X86] Fix DecodeVPERMVMask to handle cases where the constant pool entry has ↵Craig Topper2016-10-183-30/+24
| | | | | | | | a different type than the shuffle itself. This is especially important for 32-bit targets with 64-bit shuffle elements. llvm-svn: 284453
* [AVX-512] Fix DecodeVPERMV3Mask to handle cases where the constant pool ↵Craig Topper2016-10-183-20/+27
| | | | | | | | | | | | | | entry has a different type than the shuffle itself. Summary: This is especially important for 32-bit targets with 64-bit shuffle elements.This is similar to how PSHUFB and VPERMIL handle the same problem. Reviewers: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25666 llvm-svn: 284451
* [AVX-512] Add support for decoding shuffle mask from constant pool for ↵Craig Topper2016-10-181-24/+53
| | | | | | masked VPERMILPS/PD. llvm-svn: 284450
* Fix differences in codegen between Linux and Windows toolchainsMandeep Singh Grang2016-10-182-4/+7
| | | | | | | | | | | | | | | | | Summary: There are differences in codegen between Linux and Windows due to: 1. Using std::sort which uses quicksort which is a non-stable sort. 2. Iterating over Set data structure where the iteration order is non deterministic. Reviewers: arsenm, grosbach, junbuml, zinob, MatzeB Subscribers: MatzeB, wdng Differential Revision: https://reviews.llvm.org/D25695 llvm-svn: 284441
* Rename HexStyle -> HexFormatStyle, and remove a constexpr.Zachary Turner2016-10-172-23/+24
| | | | | | This should fix the remaining broken builds. llvm-svn: 284437
* Resubmit "Add support for advanced number formatting."Zachary Turner2016-10-172-89/+327
| | | | | | | | | | This resubmits commits 284425 and r284428, which were reverted in r284429 due to some infinite recursion caused by an incorrect selection of function overloads. Reproduced the failure on Linux using GCC 4.8.4, and confirmed that with the new patch the tests path on GCC as well as MSVC. So hopefully this fixes everything. llvm-svn: 284436
* [AMDGPU] Mark .note section SHF_ALLOC so lld creates a segment for itKonstantin Zhuravlyov2016-10-171-2/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D25694 llvm-svn: 284435
* [ADT] Move CachedHashString to its own header in ADT, and rename to ↵Justin Lebar2016-10-171-25/+4
| | | | | | | | | | | | | | | | CachedHashStringRef. Summary: Reclaiming the name 'CachedHashString' will let us add a type with that name that owns its value. Reviewers: timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25644 llvm-svn: 284434
* Next set of additional error checks for invalid Mach-O files for theKevin Enderby2016-10-171-0/+78
| | | | | | | | | | | | load commands that use the MachO::sub_framework_command, MachO::sub_umbrella_command, MachO::sub_library_command and MachO::sub_client_command types but are not used in llvm libObject code but used in llvm tool code. This includes the LC_SUB_FRAMEWORK, LC_SUB_UMBRELLA, LC_SUB_LIBRARY and LC_SUB_CLIENT load commands. llvm-svn: 284431
* Revert formatting changes.Zachary Turner2016-10-172-323/+88
| | | | | | | This reverts r288425 and r284428 as they are causing test crashes on some systems. llvm-svn: 284429
* Try to fix build after invalid pointer conversion.Zachary Turner2016-10-171-0/+14
| | | | llvm-svn: 284428
* [Support] Add support for "advanced" number formatting.Zachary Turner2016-10-172-88/+309
| | | | | | | | | | | | | | | raw_ostream has not afforded a lot of flexibility in terms of how to format numbers when outputting. Wrap this all up into a set of low level helper functions that can be used to output numbers with arbitrary precision, alignment, format, etc and then update raw_ostream to use these functions. This will be useful for upcoming improvements to llvm's string formatting libraries, but are still useful independently. Differential Revision: https://reviews.llvm.org/D25497 llvm-svn: 284425
* [DAG] use isConstOrConstSplat in ComputeNumSignBits to optimize SRASanjay Patel2016-10-171-1/+1
| | | | | | | | | | | | | | The scalar version of this pattern was noted in: https://reviews.llvm.org/D25485 and fixed with: https://reviews.llvm.org/rL284395 More refactoring of the constant/splat helpers is needed and will happen in follow-up patches. Differential Revision: https://reviews.llvm.org/D25685 llvm-svn: 284424
OpenPOWER on IntegriCloud