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| author | Tim Northover <tnorthover@apple.com> | 2016-10-18 20:03:48 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-10-18 20:03:48 +0000 |
| commit | 55782222c0500de1dea1aeee40e1fdf31dc853eb (patch) | |
| tree | 0ffeedf67baf97c57caeba2c375d3bb38744ce39 /llvm/lib | |
| parent | 3f18603c522c80b67db57a42bda01c6525d1acc2 (diff) | |
| download | bcm5719-llvm-55782222c0500de1dea1aeee40e1fdf31dc853eb.tar.gz bcm5719-llvm-55782222c0500de1dea1aeee40e1fdf31dc853eb.zip | |
GlobalISel: select small binary operations on AArch64.
AArch64 actually supports many 8-bit operations under the definition used by
GlobalISel: the designated information-carrying bits of a GPR32 get the right
value if you just use the normal 32-bit instruction.
llvm-svn: 284526
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index ebfd78ba2b2..eb2614d482c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -123,8 +123,13 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize) { switch (RegBankID) { case AArch64::GPRRegBankID: - switch (OpSize) { - case 32: + if (OpSize <= 32) { + assert((OpSize == 32 || (GenericOpc != TargetOpcode::G_SDIV && + GenericOpc != TargetOpcode::G_UDIV && + GenericOpc != TargetOpcode::G_LSHR && + GenericOpc != TargetOpcode::G_ASHR)) && + "operation should have been legalized before now"); + switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRWrr; @@ -149,7 +154,7 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, default: return GenericOpc; } - case 64: + } else if (OpSize == 64) { switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRXrr; @@ -676,7 +681,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { unsigned ZeroReg; unsigned NewOpc; - if (Ty == LLT::scalar(32)) { + if (Ty.isScalar() && Ty.getSizeInBits() <= 32) { NewOpc = AArch64::MADDWrrr; ZeroReg = AArch64::WZR; } else if (Ty == LLT::scalar(64)) { |
