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* [X86] Remove ISD::INSERT_SUBVECTOR handling from combineBitcastForMaskedOp. ↵Craig Topper2017-10-082-23/+133
| | | | | | | | Add isel patterns to make up for it. This will allow for some flexibility in canonicalizing bitcasts around insert_subvector. llvm-svn: 315160
* [X86] Use getConstantOperandVal to simplify some code. NFCCraig Topper2017-10-081-3/+3
| | | | llvm-svn: 315159
* [X86][SSE] Match bitcasted BUILD_VECTOR of constants for v2i64 shifts on ↵Simon Pilgrim2017-10-071-2/+2
| | | | | | | | 64-bit targets (PR34855) Extension to rL315155, generate constant shifts on 64-bits as well as 32-bits. llvm-svn: 315156
* [X86][SSE] Match bitcasted v4i32 BUILD_VECTORS for v2i64 shifts on 64-bit ↵Simon Pilgrim2017-10-071-3/+2
| | | | | | | | targets (PR34855) We were already doing this for 32-bit targets, but we can generate these on 64-bits as well. llvm-svn: 315155
* [SelectionDAG} Use KnownBits::isUnknown and hasConflict. NFCCraig Topper2017-10-071-8/+8
| | | | llvm-svn: 315154
* [X86] Add X86ISD::CMOV to computeKnownBitsForTargetNode and ↵Craig Topper2017-10-071-0/+20
| | | | | | | | | | | | | | | | ComputeNumSignBitsForTargetNode. Summary: Implementations based on ISD::SELECT. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38663 llvm-svn: 315153
* [X86][SSE] Improve shuffling combining with horizontal operationsSimon Pilgrim2017-10-071-33/+33
| | | | | | | | | | Recognise cases when we can merge the shuffles with their horizontal (HADD/HSUB/PACK) instruction inputs. Replaces an older implementation which performed some of this during lowering, expanding an existing target shuffle combine stage instead. Differential Revision: https://reviews.llvm.org/D38506 llvm-svn: 315150
* [X86] Update an outdated comment about SjLjMartin Storsjo2017-10-071-6/+2
| | | | | | | | | The SjLj intrinsics in the X86 backend are intended for use with SjLj exception handling as well, since SVN r271244. Differential Revision: https://reviews.llvm.org/D38532 llvm-svn: 315146
* [X86] Correct result type for the flag result of RDSEED and RDRAND nodes. ↵Craig Topper2017-10-071-2/+2
| | | | | | | | Correct the CC type for the CMOV used with RDSEED/RDRAND. The flag result was MVT::Glue, but should be MVT::i32. The CC type was MVT::i8, but should be MVT::i32. llvm-svn: 315145
* [MachineOutliner] Disable outlining from LinkOnceODRs by defaultJessica Paquette2017-10-076-15/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Say you have two identical linkonceodr functions, one in M1 and one in M2. Say that the outliner outlines A,B,C from one function, and D,E,F from another function (where letters are instructions). Now those functions are not identical, and cannot be deduped. Locally to M1 and M2, these outlining choices would be good-- to the whole program, however, this might not be true! To mitigate this, this commit makes it so that the outliner sees linkonceodr functions as unsafe to outline from. It also adds a flag, -enable-linkonceodr-outlining, which allows the user to specify that they want to outline from such functions when they know what they're doing. Changing this handles most code size regressions in the test suite caused by competing with linker dedupe. It also doesn't have a huge impact on the code size improvements from the outliner. There are 6 tests that regress > 5% from outlining WITH linkonceodrs to outlining WITHOUT linkonceodrs. Overall, most tests either improve or are not impacted. Not outlined vs outlined without linkonceodrs: https://hastebin.com/raw/qeguxavuda Not outlined vs outlined with linkonceodrs: https://hastebin.com/raw/edepoqoqic Outlined with linkonceodrs vs outlined without linkonceodrs: https://hastebin.com/raw/awiqifiheb Numbers generated using compare.py with -m size.__text. Tests run for AArch64 with -Oz -mllvm -enable-machine-outliner -mno-red-zone. llvm-svn: 315136
* [InstCombine] use correct type when propagating constant condition in ↵Sanjay Patel2017-10-061-2/+3
| | | | | | simplifyDivRemOfSelectWithZeroOp (PR34856) llvm-svn: 315130
* [InstCombine] rename SimplifyDivRemOfSelect to be clearer, add comments, ↵Sanjay Patel2017-10-062-20/+20
| | | | | | | | | simplify code; NFCI There's at least one bug here - this code can fail with vector types (PR34856). It's also being called for FREM; I'm still trying to understand how that is valid. llvm-svn: 315127
* [AVX512] Fix TERNLOG when folding broadcastCameron McInally2017-10-061-4/+4
| | | | | | | | | Patch to fix ternlog instructions with a folded broadcast. The broadcast decorator, e.g. {1toX}, was missing. Differential Revision: https://reviews.llvm.org/D38649 llvm-svn: 315122
* [dwarfdump] Verify that unit type matches root DIEJonas Devlieghere2017-10-061-8/+24
| | | | | | | | | | | | | This patch adds two new verifiers: - It checks that the root DIE of a CU is actually a valid unit DIE. (based on its tag) - For DWARF5 which contains a unit type int he CU header, it checks that this matches the type of the unit DIE. Differential revision: https://reviews.llvm.org/D38453 llvm-svn: 315121
* Revert "Roll forward r314928"Reid Kleckner2017-10-062-238/+0
| | | | | | | | | | | | | | | | | | | | This appears to be miscompiling Clang, as shown on two Windows bootstrap bots: http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7611 http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/6870 Nothing else is in the blame list. Both emit errors on this valid code in the Windows ucrt headers: C:\...\ucrt\malloc.h:95:32: error: invalid operands to binary expression ('char *' and 'int') _Ptr = (char*)_Ptr + _ALLOCA_S_MARKER_SIZE; ~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~ I am attempting to reproduce this now. This reverts r315044 llvm-svn: 315108
* [PEI] Remove required properties and use 'if' instead of std::functionReid Kleckner2017-10-061-49/+23
| | | | | | | | | | | | | | | | | | Summary: After r303360, we initialize UsesCalleeSaves in runOnMachineFunction, which runs after getRequiredProperties. UsesCalleeSaves was initialized to 'false', so getRequiredProperties would always return an empty set. We don't have a TargetMachine available early anymore after r303360. Just removing the requirement of NoVRegs seems to make things work, so let's do that. Reviewers: thegameg, dschuff, MatzeB Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D38597 llvm-svn: 315089
* Bitcode: add an auto-upgrade for LTO section nameSaleem Abdulrasool2017-10-063-1/+31
| | | | | | | | | | | The bitcode reader looks specifically for `__DATA, __objc_catlist` as a section name. However, SVN r304661 removed the spaces (the two names are functionally equivalent but do not compare equally lexicographically). This causes compatibility issues. Add an auto-upgrade path for removing the spaces as well as use the new name in the LTO plugin. llvm-svn: 315086
* [AMDGPU] New 64 bit div/rem expansionStanislav Mekhanoshin2017-10-061-19/+151
| | | | | | | | | | | Old expansion was 20 VGPRs, 78 SGPRs and ~380 instructions. This expansion is 11 VGPRs, 12 SGPRs and ~120 instructions. Passes OpenCL conformance test_integer_ops quick_[u]long_math Differential Revision: https://reviews.llvm.org/D38607 llvm-svn: 315081
* [MC] Use unique_ptr to manage WinFrameInfos, NFCReid Kleckner2017-10-062-16/+12
| | | | | | | | The FrameInfo cannot be stored directly in the vector because chained frames may refer to parent frames, so we need pointers that are stable across a vector resize. llvm-svn: 315080
* Support: Rewrite Windows implementation of sys::fs::rename to be more POSIXy.Peter Collingbourne2017-10-061-47/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of rename uses ReplaceFile if the destination file already exists. According to the documentation for ReplaceFile, the source file is opened without a sharing mode. This means that there is a short interval of time between when ReplaceFile renames the file and when it closes the file during which the destination file cannot be opened. This behaviour is not POSIX compliant because rename is supposed to be atomic. It was also causing intermittent link failures when linking with a ThinLTO cache; the ThinLTO cache implementation expects all cache files to be openable. This patch addresses that problem by re-implementing rename using CreateFile and SetFileInformationByHandle. It is roughly a reimplementation of ReplaceFile with a better sharing policy as well as support for renaming in the case where the destination file does not exist. This implementation is still not fully POSIX. Specifically in the case where the destination file is open at the point when rename is called, there will be a short interval of time during which the destination file will not exist. It isn't clear whether it is possible to avoid this using the Windows API. Differential Revision: https://reviews.llvm.org/D38570 llvm-svn: 315079
* Directly return promoted direct call instead of rely on stripPointerCast.Dehao Chen2017-10-062-11/+15
| | | | | | | | | | | | | | Summary: stripPointerCast is not reliably returning the value that's being type-casted. Instead it may look further at function attributes to further propagate the value. Instead of relying on stripPOintercast, the more reliable solution is to directly use the pointer to the promoted direct call. Reviewers: tejohnson, davidxl Reviewed By: tejohnson Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D38603 llvm-svn: 315077
* [ARM] GlobalISel: Select shiftsDiana Picus2017-10-061-0/+16
| | | | | | | | | Unfortunately TableGen doesn't handle this yet: Unable to deduce gMIR opcode to handle Src (which is a leaf). Just add some temporary hand-written code to generate the proper MOVsr. llvm-svn: 315071
* [ARM] GlobalISel: Map shift operands to GPRsDiana Picus2017-10-061-0/+3
| | | | llvm-svn: 315067
* [llvm-dsymutil] Add support for __swift_ast MachO DWARF sectionFrancis Ricci2017-10-061-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging, and which contains a byte-for-byte dump of the swiftmodule file. Add this feature to llvm-dsymutil. Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of `__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil (Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the __swift_ast section). Reviewers: aprantl, friss Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D38504 llvm-svn: 315066
* [ARM] GlobalISel: Mark shifts as legal for s32Diana Picus2017-10-061-0/+3
| | | | | | | The new legalize combiner introduces shifts all over the place, so we should support them sooner rather than later. llvm-svn: 315064
* [SystemZ] Enable machine scheduler.Jonas Paulsson2017-10-061-0/+5
| | | | | | | | | | | | | The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
* Revert "[MergeICmps] Disable mergeicmps if the target does not want to ↵Clement Courbet2017-10-061-36/+12
| | | | | | | | | | handle memcmp expansion." Still a few stability issues on windows. This reverts commit 67e3db9bc121ba244e20337aabc7cf341a62b545. llvm-svn: 315058
* Re-land "[MergeICmps] Disable mergeicmps if the target does not want to ↵Clement Courbet2017-10-061-12/+36
| | | | | | | | | | handle memcmp expansion." (fixed unit tests by making comparisons stable) This reverts commit 1b2d359ce256fd6737da4e93833346a0bd6d7583. llvm-svn: 315056
* Roll forward r314928Xinliang David Li2017-10-062-0/+238
| | | | | | | Fixed ThinLTO bootstrap failure : track new bitcast per incomingVal. Added new tests. llvm-svn: 315044
* [PM] Retire disable unit-at-a-time switch.Davide Italiano2017-10-061-33/+24
| | | | | | | | | | | | This is a vestige from the GCC-3 days, which disables IPO passes when set. I don't think anybody actually uses it as there are several IPO passes which still run with this flag set and nobody complained/noticed. This reduces the delta between current and new pass manager and allows us to easily review the difference when we decide to flip the switch (or audit which passes should run, FWIW). llvm-svn: 315043
* [CodeExtractor] Fix multiple bugs under certain shape of extracted regionJakub Kuderski2017-10-061-77/+31
| | | | | | | | | | | | | | | | Summary: If the extracted region has multiple exported data flows toward the same BB which is not included in the region, correct resotre instructions and PHI nodes won't be generated inside the exitStub. The solution is simply put the restore instructions right after the definition of output values instead of putting in exitStub. Unittest for this bug is included. Author: myhsu Reviewers: chandlerc, davide, lattner, silvas, davidxl, wmi, kuhar Subscribers: dberlin, kuhar, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D37902 llvm-svn: 315041
* NewGVN: Factor out duplicate parts of OpIsSafeForPHIOfOpsDaniel Berlin2017-10-061-45/+31
| | | | llvm-svn: 315040
* Revert "[llvm-dsymutil] Add support for __swift_ast MachO DWARF section"Francis Ricci2017-10-051-4/+0
| | | | | | | | Breaks aarch64 builders This reverts commit r315014. llvm-svn: 315034
* [MBP] Remove an invalid assert.Xin Tong2017-10-051-6/+0
| | | | | | | | | | | | The patch that this assert comes with is fixing a bug in MBP. The assert is invalid however. Thanks to @sergey.k.okunev for finding this Currently this fails SPECCPU2006 LTO. I will add a test case when I do more investigation and have one. llvm-svn: 315032
* ModuleUtils: Stop using comdat members to generate unique module ids.Peter Collingbourne2017-10-051-1/+1
| | | | | | | | | | | It is possible for two modules to define the same set of external symbols without causing a duplicate symbol error at link time, as long as each of the symbols is a comdat member. So we cannot use them as part of a unique id for the module. Differential Revision: https://reviews.llvm.org/D38602 llvm-svn: 315026
* [X86] Extract CATCHRET handling from emitEpilogue, NFCReid Kleckner2017-10-052-33/+42
| | | | llvm-svn: 315023
* [WebAssembly] Add the rest of the atomic loadsDerek Schuff2017-10-054-56/+198
| | | | | | | | | | Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
* [InstCombine] improve folds for icmp gt/lt (shr X, C1), C2Sanjay Patel2017-10-051-37/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can always eliminate the shift in: icmp gt/lt (shr X, C1), C2 --> icmp gt/lt X, C' This patch was supposed to just be an efficiency improvement because we were doing this 3-step process to fold: IC: Visiting: %c = icmp ugt i4 %s, 1 IC: ADD: %s = lshr i4 %x, 1 IC: ADD: %1 = udiv i4 %x, 2 IC: Old = %c = icmp ugt i4 %1, 1 New = <badref> = icmp uge i4 %x, 4 IC: ADD: %c = icmp uge i4 %x, 4 IC: ERASE %2 = icmp ugt i4 %1, 1 IC: Visiting: %c = icmp uge i4 %x, 4 IC: Old = %c = icmp uge i4 %x, 4 New = <badref> = icmp ugt i4 %x, 3 IC: ADD: %c = icmp ugt i4 %x, 3 IC: ERASE %2 = icmp uge i4 %x, 4 IC: Visiting: %c = icmp ugt i4 %x, 3 IC: DCE: %1 = udiv i4 %x, 2 IC: ERASE %1 = udiv i4 %x, 2 IC: DCE: %s = lshr i4 %x, 1 IC: ERASE %s = lshr i4 %x, 1 IC: Visiting: ret i1 %c When we could go directly to canonical icmp form: IC: Visiting: %c = icmp ugt i4 %s, 1 IC: Old = %c = icmp ugt i4 %s, 1 New = <badref> = icmp ugt i4 %x, 3 IC: ADD: %c = icmp ugt i4 %x, 3 IC: ERASE %1 = icmp ugt i4 %s, 1 IC: ADD: %s = lshr i4 %x, 1 IC: DCE: %s = lshr i4 %x, 1 IC: ERASE %s = lshr i4 %x, 1 IC: Visiting: %c = icmp ugt i4 %x, 3 ...but then I noticed that the folds were incomplete too: https://godbolt.org/g/aB2hLE Here are attempts to prove the logic with Alive: https://rise4fun.com/Alive/92o Name: lshr_ult Pre: ((C2 << C1) u>> C1) == C2 %sh = lshr i8 %x, C1 %r = icmp ult i8 %sh, C2 => %r = icmp ult i8 %x, (C2 << C1) Name: ashr_slt Pre: ((C2 << C1) >> C1) == C2 %sh = ashr i8 %x, C1 %r = icmp slt i8 %sh, C2 => %r = icmp slt i8 %x, (C2 << C1) Name: lshr_ugt Pre: (((C2+1) << C1) u>> C1) == (C2+1) %sh = lshr i8 %x, C1 %r = icmp ugt i8 %sh, C2 => %r = icmp ugt i8 %x, ((C2+1) << C1) - 1 Name: ashr_sgt Pre: (C2 != 127) && ((C2+1) << C1 != -128) && (((C2+1) << C1) >> C1) == (C2+1) %sh = ashr i8 %x, C1 %r = icmp sgt i8 %sh, C2 => %r = icmp sgt i8 %x, ((C2+1) << C1) - 1 Name: ashr_exact_sgt Pre: ((C2 << C1) >> C1) == C2 %sh = ashr exact i8 %x, C1 %r = icmp sgt i8 %sh, C2 => %r = icmp sgt i8 %x, (C2 << C1) Name: ashr_exact_slt Pre: ((C2 << C1) >> C1) == C2 %sh = ashr exact i8 %x, C1 %r = icmp slt i8 %sh, C2 => %r = icmp slt i8 %x, (C2 << C1) Name: lshr_exact_ugt Pre: ((C2 << C1) u>> C1) == C2 %sh = lshr exact i8 %x, C1 %r = icmp ugt i8 %sh, C2 => %r = icmp ugt i8 %x, (C2 << C1) Name: lshr_exact_ult Pre: ((C2 << C1) u>> C1) == C2 %sh = lshr exact i8 %x, C1 %r = icmp ult i8 %sh, C2 => %r = icmp ult i8 %x, (C2 << C1) We did something similar for 'shl' in D28406. Differential Revision: https://reviews.llvm.org/D38514 llvm-svn: 315021
* [Hexagon] Make PS_fi and PS_fia extendable (they both expand to A2_addi)Krzysztof Parzyszek2017-10-051-3/+6
| | | | llvm-svn: 315019
* Annotate VP prof on indirect call if it is ICPed in the profiled binary.Dehao Chen2017-10-051-1/+3
| | | | | | | | | | | | | | Summary: In SamplePGO, when an indirect call is promoted in the profiled binary, before profile annotation, it will be promoted and inlined. For the original indirect call, the current implementation will not mark VP profile on it. This is an issue when profile becomes stale. This patch annotates VP prof on indirect calls during annotation. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38477 llvm-svn: 315016
* [llvm-dsymutil] Add support for __swift_ast MachO DWARF sectionFrancis Ricci2017-10-051-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging, and which contains a byte-for-byte dump of the swiftmodule file. Add this feature to llvm-dsymutil. Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of `__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil (Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the __swift_ast section). Reviewers: aprantl, friss Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D38504 llvm-svn: 315014
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-054-56/+81
| | | | | | | | | | | | | | | The new format is changeAddrMode_xx_yy, where xx is the current mode, and yy is the new one. Old name: New name: getBaseWithImmOffset changeAddrMode_abs_io getAbsoluteForm changeAddrMode_io_abs getBaseWithRegOffset changeAddrMode_io_rr xformRegToImmOffset changeAddrMode_rr_io getBaseWithLongOffset changeAddrMode_rr_ur getRegShlForm changeAddrMode_ur_rr llvm-svn: 315013
* Revert "[llvm-dsymutil] Add support for __swift_ast MachO DWARF section"Francis Ricci2017-10-051-4/+0
| | | | | | This reverts commit r315004, because of a failing test on non-apple platforms llvm-svn: 315009
* [llvm-dsymutil] Add support for __swift_ast MachO DWARF sectionFrancis Ricci2017-10-051-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging, and which contains a byte-for-byte dump of the swiftmodule file. Add this feature to llvm-dsymutil. Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of `__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil (Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the __swift_ast section). Reviewers: aprantl, friss Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D38504 llvm-svn: 315004
* [NewPassManager] Run global dead code elimination after the inliner.Davide Italiano2017-10-051-0/+1
| | | | | | | | | This is the same exact change we did for the current pass manager in rL314997, but the new pass manager pipeline already happened to run GlobalOpt after the inliner, so we just insert a run of GDCE here. llvm-svn: 315003
* [X86] Simplify X86 epilogue frame size calculation, NFCReid Kleckner2017-10-051-39/+28
| | | | | | | | | | | | | | | | | | | | | Sink the insertion of "pop ebp" out of the frame size calculation branches. They all check for HasFP. Our handling of CLEANUPRET and CATCHRET was equivalent, both are funclets and use the same frame size. We can eliminate the CLEANUPRET case. Hoist the hasFP(MF) query into a local bool. Rename TargetMBB to CatchRetTarget to be more descriptive. Eliminate the Optional<unsigned> RetOpcode local, now that it has one use. It's only a net savings of 10 lines, but hopefully it's *slightly* more readable. llvm-svn: 315000
* [PassManager] Improve the interaction between -O2 and ThinLTO.Davide Italiano2017-10-051-13/+11
| | | | | | | Run GDCE slightly later so that we don't have to repeat it twice when preparing for Thin. Thanks to Mehdi for the suggestion. llvm-svn: 314999
* [PassManager] Run global optimizations after the inliner.Davide Italiano2017-10-051-0/+14
| | | | | | | | | | | | | | | The inliner performs some kind of dead code elimination as it goes, but there are cases that are not really caught by it. We might at some point consider teaching the inliner about them, but it is OK for now to run GlobalOpt + GlobalDCE in tandem as their benefits generally outweight the cost, making the whole pipeline faster. This fixes PR34652. Differential Revision: https://reviews.llvm.org/D38154 llvm-svn: 314997
* [SparsePropagation] Move member definitions to header (NFC)Matthew Simpson2017-10-052-365/+0
| | | | | | | | | AbstractLatticeFunction and SparseSolver are class templates parameterized by a lattice value, so we need to move these member functions over to the header. Differential Revision: https://reviews.llvm.org/D38561 llvm-svn: 314996
* [mips] implement .set dspr2 directivePetar Jovanovic2017-10-053-0/+14
| | | | | | | | | | | | Implement .set dspr2 directive with appropriate feature bits. This directive is a counterpart of -mattr=dspr2 command line option with the exception that it does not influence elf header flags. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38537 llvm-svn: 314994
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