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* [X86] Make sure all the classes declare in the Haswell scheduler model are ↵Craig Topper2018-04-021-66/+66
| | | | | | | | prefixed with HW. The tablegen files all share a namespace so we shouldn't use a generic names in a specific scheduler model. llvm-svn: 328955
* [X86] Give VINSERTPS the same intinerary as INSERTPS.Craig Topper2018-04-021-3/+4
| | | | llvm-svn: 328954
* Add C API bindings for DIBuilder 'Type' APIsHarlan Haskins2018-04-021-1/+190
| | | | | | | | | | This patch adds a set of unstable C API bindings to the DIBuilder interface for creating structure, function, and aggregate types. This patch also removes the existing implementations of these functions from the Go bindings and updates the Go API to fit the new C APIs. llvm-svn: 328953
* [X86] Cleanup ADCX/ADOX instruction definitions.Craig Topper2018-04-011-29/+45
| | | | | | Give them both the same itineraries. Add hasSideEffects = 0 to ADOX since they don't have patterns. Rename source operands to $src1 and $src2 instead of $src0 and $src. Add ReadAfterLd to the memory form SchedRW. llvm-svn: 328952
* [AArch64] Reserve x18 register on FuchsiaPetr Hosek2018-04-011-2/+2
| | | | | | | | This register is reserved as a platform register on Fuchsia. Differential Revision: https://reviews.llvm.org/D45105 llvm-svn: 328950
* [DebugCounter] Make -debug-counter cl::Hidden.Craig Topper2018-04-011-1/+1
| | | | llvm-svn: 328948
* [LegacyPassManager] Make 'print-module-scope' cl::Hidden like the rest of ↵Craig Topper2018-04-011-1/+1
| | | | | | the printing options. llvm-svn: 328947
* [X86] Give ADC8/16/32/64mi the same scheduling information as ↵Craig Topper2018-04-014-22/+10
| | | | | | | | ADC8/16/32/64mr and SBB8/16/32/64mi. It doesn't make a lot of sense that it would be different. llvm-svn: 328946
* [x86] Correct the operand structure of the ADOX instruction.Chandler Carruth2018-04-011-19/+11
| | | | | | | | | | | | | | | This also moves to define it in the same way as ADCX which seems to use constraints a bit better. This is pulled out of the review for reducing the use of popf for restoring EFLAGS, but is independent. There are still more problems with our definitions for these instructions that Craig is going to look at but this is at least less broken and he can start from this to improve them more fully. Thanks to Craig for the review here. llvm-svn: 328945
* [x86] Expose more of the condition conversion routines in the public APIChandler Carruth2018-04-012-7/+13
| | | | | | | | for X86's instruction information. I've now got a second patch under review that needs these same APIs. This bit is nicely orthogonal and obvious, so landing it. NFC. llvm-svn: 328944
* AMDGPU: Make isIntrinsicSourceOfDivergence table-drivenNicolai Haehnle2018-04-012-47/+63
| | | | | | | | | | | | | | | | Summary: This is in preparation for the new dimension-aware image intrinsics, which I'd rather not have to list here by hand. Change-Id: Iaa16e3a635a11283918ce0d9e1e618591b0bf6fa Reviewers: arsenm, rampitec, b-sumner Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D44938 llvm-svn: 328939
* AMDGPU: Make getTgtMemIntrinsic table-driven for resource-based intrinsicsNicolai Haehnle2018-04-016-214/+91
| | | | | | | | | | | | | | | | | | Summary: Avoids having to list all intrinsics manually. This is in preparation for the new dimension-aware image intrinsics, which I'd rather not have to list here by hand. Change-Id: If7ced04998397ef68c4cb8f7de66b5050fb767e5 Reviewers: arsenm, rampitec, b-sumner Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D44937 llvm-svn: 328938
* [DebugInfo] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-014-9/+9
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: echristo, zturner, samsonov Reviewed By: echristo Subscribers: JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D45134 llvm-svn: 328935
* [ThinLTO] Add an import cutoff for debugging/triagingTeresa Johnson2018-04-011-0/+13
| | | | | | | | | | | | | | Summary: Adds -import-cutoff=N which will stop importing during the thin link after N imports. Default is -1 (no limit). Reviewers: wmi Subscribers: inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D45127 llvm-svn: 328934
* [LoopRotate] Rotate loops with loop exiting latchesDavid Green2018-04-011-2/+24
| | | | | | | | | | | If a loop has a loop exiting latch, it can be profitable to rotate the loop if it leads to the simplification of a phi node. Perform rotation in these cases even if loop rotate itself didnt simplify the loop to get there. Differential Revision: https://reviews.llvm.org/D44199 llvm-svn: 328933
* [X86] Don't check for folding into a store when deciding if we can promote ↵Craig Topper2018-04-011-2/+4
| | | | | | | | an i16 mul. There's no RMW mul operation. llvm-svn: 328931
* [X86] Check if the load and store are to the same pointer before preventing ↵Craig Topper2018-04-011-3/+14
| | | | | | i16 RMW shifts and subtracts from being promoted. llvm-svn: 328930
* [X86] Allow i16 subtracts to be promoted if the load is on the LHS and its ↵Craig Topper2018-04-011-4/+4
| | | | | | not being stored. llvm-svn: 328928
* [X86] Remove unneeded temporary variable. NFCCraig Topper2018-04-011-6/+2
| | | | | | This Promote flag was alwasys set to true except in the default case. But in the default case we don't need to set PVT and can just return false. llvm-svn: 328926
* [Analysis] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-018-21/+21
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer D44363 for a list of all the required patches. Reviewers: sanjoy, dexonsmith, hfinkel, RKSimon Reviewed By: dexonsmith Subscribers: david2050, llvm-commits Differential Revision: https://reviews.llvm.org/D44944 llvm-svn: 328925
* [DAGCombine] (float)((int) f) --> ftrunc (PR36617)Sanjay Patel2018-03-311-0/+18
| | | | | | | | | | fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC, so replace a pair of casts with the equivalent node. We don't have to account for special cases (NaN, INF) because out-of-range casts are undefined. Differential Revision: https://reviews.llvm.org/D44909 llvm-svn: 328921
* [X86][Btver2] Add MMX_PSHUFB to the JWritePSHUFB InstRW entriesSimon Pilgrim2018-03-311-2/+2
| | | | llvm-svn: 328918
* Fix trailing whitespace. NFCI.Simon Pilgrim2018-03-311-1/+1
| | | | llvm-svn: 328917
* [MIR-Canon] Adding support for local idempotent instruction hoisting.Puyan Lotfi2018-03-311-5/+116
| | | | llvm-svn: 328915
* [X86] Add SchedRW for PMULLDCraig Topper2018-03-3111-46/+11
| | | | | | | | | | | | | | | | | | | Summary: It seems many CPUs don't implement this instruction as well as the other vector multiplies. Often using a multi uop flow. Silvermont in particular has a 7 uop flow with 11 cycle throughput. Sandy Bridge implements it as a single uop with 5 cycle latency and 1 cycle throughput. But Haswell and later use 2 uops with 10 cycle latency and 2 cycle throughput. This patch adds a new X86SchedWritePair we can use to tag this instruction separately. I've provided correct information for Silvermont, Btver2, and Sandy Bridge. I've removed the InstRWs for SandyBridge. I've left Haswell/Broadwell/Skylake InstRWs in place because I wasn't sure how to account for the different load latency between 128 and 256 bits. I also left Znver1 InstRWs in place because the existing values don't match Agner's spreadsheet. I also left a FIXME in the SandyBridge model because it being used for the "generic" model is too optimistic for the 256/512-bit versions since those are multiple uops on all known CPUs. Reviewers: RKSimon, GGanesh, courbet Reviewed By: RKSimon Subscribers: gchatelet, gbedwell, andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D44972 llvm-svn: 328914
* [ThinLTO] Add an option to force summary call edges cold for debuggingTeresa Johnson2018-03-312-2/+23
| | | | | | | | | | | | | | Summary: Useful to selectively disable importing into specific modules for debugging/triaging/workarounds. Reviewers: eraman Subscribers: inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D45062 llvm-svn: 328909
* Fix a bunch of typoes. NFCFangrui Song2018-03-3012-17/+16
| | | | llvm-svn: 328907
* Prevent data races in concurrent ThinLTO processes.Ekaterina Romanova2018-03-301-17/+14
| | | | | | | | | | | | Make sure ThinLTO with caching doesn't use non-atomic writes to the cache file (to prevent data races and cache files corruption). 1. Place temp file to the same place where the caching directory is (instead of creating it the directory pointed to by TMP/TEMP variable). This will help to prevent using non-atomic rename and falling back to non-atomic "direct" write to the cache file. 2. if rename failed do not write to the cache file directly (direct write to the file is non-atomic and could cause data race conditions). 3. if cache file doesn't exist (e.g., because 'rename' failed or because some other reasons), bypass using the cache altogether. Differential Revision: https://reviews.llvm.org/D45076 llvm-svn: 328904
* [WebAssembly] Register wasm passes with the PassRegistryJacob Gravelle2018-03-3021-4/+107
| | | | | | | | | | | | | | Summary: This exposes WebAssembly passes for use on the command line (as arguments to -print-before and the like). Reviewers: dschuff, sunfish Subscribers: MatzeB, jfb, sbc100, llvm-commits, aheejin Differential Revision: https://reviews.llvm.org/D45103 llvm-svn: 328901
* [Hexagon] Reduce excessive indentation in .s outputKrzysztof Parzyszek2018-03-302-16/+8
| | | | llvm-svn: 328898
* [Hexagon] Avoid creating invalid offsets in packetizerKrzysztof Parzyszek2018-03-301-0/+3
| | | | | | | | | | Two memory instructions with a dependency only on the address register between the two (the first one of them being post-incrememnt) can be packetized together after the offset on the second was updated to the incremement value. Make sure that the new offset is valid for the instruction. llvm-svn: 328897
* [X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts andAndrea Di Biagio2018-03-301-8/+17
| | | | | | | | | VSQRT instructions. There were still a few AVX instructions with an incorrect number of opcodes. These should be fixed now. llvm-svn: 328892
* DataFlowSanitizer: wrappers of functions with local linkage should have the ↵Peter Collingbourne2018-03-301-1/+9
| | | | | | | | | | | | | | same linkage as the function being wrapped This patch resolves link errors when the address of a static function is taken, and that function is uninstrumented by DFSan. This change resolves bug 36314. Patch by Sam Kerner! Differential Revision: https://reviews.llvm.org/D44784 llvm-svn: 328890
* [MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi2018-03-309-11/+79
| | | | llvm-svn: 328887
* [X86][BtVer2] Fix the number of uOps for horizontal operations.Andrea Di Biagio2018-03-301-0/+2
| | | | llvm-svn: 328886
* [NVPTX] Enable StructuredCFG for NVPTXTim Shen2018-03-301-0/+10
| | | | | | | | | | | | | | | | | Summary: Make NVPTX require structured CFG. Added a temporary flag to "roll back" the behavior for easy deployment. Combined with D45008, this fixes several internal Nvidia GPU test failures that we suspect to be ptxas miscompiles (PR27738). Reviewers: jlebar Subscribers: jholewinski, sanjoy, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D45070 llvm-svn: 328885
* [BlockPlacement] Disable block placement tail duplciation in structured CFG.Tim Shen2018-03-301-6/+11
| | | | | | | | | | | | | | | | | | | | | | Summary: Tail duplication easily breaks the structure of CFG, e.g. duplicating on a region entry. If the structure is intended to be preserved, then we may want to configure tail duplication, or disable it for structured CFG. From our benchmark results disabling it doesn't cause performance regression. Notice that this currently affects AMDGPU backend. In the next patch, I also plan to turn on requiresStructuredCFG for NVPTX. All unit tests still pass. Reviewers: jlebar, arsenm Subscribers: jholewinski, sanjoy, wdng, tpr, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45008 llvm-svn: 328884
* [LLVM-C] Finish exception instruction bindings - Round 2Robert Widmann2018-03-301-2/+92
| | | | | | | | | | | | | | | | | | | Summary: Previous revision caused a leak in the echo test that got caught by the ASAN bots because of missing free of the handlers array and was reverted in r328759. Resubmitting the patch with that correction. Add support for cleanupret, catchret, catchpad, cleanuppad and catchswitch and their associated accessors. Test is modified from SimplifyCFG because it contains many diverse usages of these instructions. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits, vlad.tsyrklevich Differential Revision: https://reviews.llvm.org/D45100 llvm-svn: 328883
* [llvm-pdbutil] Dig deeper into the PDB and DBI streams when explaining.Zachary Turner2018-03-301-13/+9
| | | | | | | | | This will show more detail when using `llvm-pdbutil explain` on an offset in the DBI or PDB streams. Specifically, it will dig into individual header fields and substreams to give a more precise description of what the byte represents. llvm-svn: 328878
* [WebAssembly] Refactor tablegen for store instructions (NFC)Derek Schuff2018-03-301-194/+115
| | | | | | | | Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
* Revert "peel loops with runtime small trip counts"Krzysztof Parzyszek2018-03-302-14/+1
| | | | | | This reverts commit r328854, it breaks some Hexagon tests. llvm-svn: 328875
* [AMDGPU] Fixed some instructions latenciesStanislav Mekhanoshin2018-03-302-13/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D45073 llvm-svn: 328874
* [SelectionDAG] Removing FABS folding from DAGCombinerSanjay Patel2018-03-301-18/+0
| | | | | | | | | | | | | | The code has bugs dealing with -0.0. Since D44550 introduced FABS pattern folding in InstCombine, this patch removes the now-redundant code that causes https://bugs.llvm.org/show_bug.cgi?id=36600. Patch by Mikhail Dvoretckii! Differential Revision: https://reviews.llvm.org/D44683 llvm-svn: 328872
* [Hexagon] Recognize and handle :endloop01Krzysztof Parzyszek2018-03-303-13/+24
| | | | llvm-svn: 328870
* [Hexagon] Fix printing :mem_noshuf on compiler-generated packetsKrzysztof Parzyszek2018-03-301-2/+7
| | | | llvm-svn: 328869
* [X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds andAndrea Di Biagio2018-03-301-9/+14
| | | | | | | | | most vector logic instructions. Fixed a few InstRW that forgot to specify a ReadAfterLd for the register input operand. llvm-svn: 328867
* [Hexagon] Remove unused scheduling classesKrzysztof Parzyszek2018-03-301-485/+0
| | | | llvm-svn: 328866
* [Hexagon] Pass pointer to SelectionDAG to dump functionsKrzysztof Parzyszek2018-03-301-5/+5
| | | | llvm-svn: 328864
* Revert "[LLVM-C] Finish exception instruction bindings"Vlad Tsyrklevich2018-03-301-92/+2
| | | | | | This reverts commit r328759. It was causing LSan failures on sanitizer-x86_64-linux-bootstrap llvm-svn: 328858
* [AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE.Michael Bedy2018-03-301-7/+67
| | | | | | | | | | | | | | | | | | | | | | Summary: The phase attempts to transform operations that extract a portion of a value into an SDWA src operand in cases where that value is used only once. It was not prepared for this use to be the preserved portion of a value for dst:UNUSED_PRESERVE, resulting in a crash or assert. This change either rejects the illegal SDWA attempt, or in the case where dst:WORD_1 and the src_sel would be WORD_0, removes the unneeded extract instruction. Reviewers: arsenm, #amdgpu Reviewed By: arsenm, #amdgpu Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D44364 llvm-svn: 328856
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