summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* CMake: Turned some libraries into partially linked objects. CorrectedOscar Fuentes2008-10-225-5/+5
| | | | | | names of LLVMCore and ARMCodeGen. llvm-svn: 57943
* Adjust comments for pedantic satisfaction.Dale Johannesen2008-10-221-9/+9
| | | | llvm-svn: 57940
* CMake: updated lib/VMCore/CMakeLists.txtOscar Fuentes2008-10-211-0/+1
| | | | llvm-svn: 57937
* Privatize PrintModulePass and PrintFunctionPass and addDaniel Dunbar2008-10-213-11/+100
| | | | | | | createPrintModulePass and createPrintFunctionPass. - So clients who compile w/o RTTI can use them. llvm-svn: 57933
* Add comments to explain uint64->f64 algorithm,Dale Johannesen2008-10-211-0/+35
| | | | | | well, sort of. (Algorithm by Ian Ollmann.) llvm-svn: 57932
* Add an SSE2 algorithm for uint64->f64 conversion.Dale Johannesen2008-10-213-2/+86
| | | | | | | | | | The same one Apple gcc uses, faster. Also gets the extreme case in gcc.c-torture/execute/ieee/rbug.c correct which we weren't before; this is not sufficient to get the test to pass though, there is another bug. llvm-svn: 57926
* Fix SelectionDAGBuild lowering of Select instructions toDan Gohman2008-10-211-8/+22
| | | | | | | handle first-class aggregate values. Also, fix a bug in the Ret handling for empty aggregates. llvm-svn: 57925
* Clear raw_fd_ostream error string on success and explain behavior inDaniel Dunbar2008-10-211-3/+6
| | | | | | | | documentation. Add C++ header marker. llvm-svn: 57923
* Implement the optimized FCMP_OEQ/FCMP_UNE code for x86 fast-isel.Dan Gohman2008-10-211-0/+12
| | | | llvm-svn: 57915
* use pre-UAL mnemonics for push/pop for compilaton callback functionJim Grosbach2008-10-211-2/+2
| | | | llvm-svn: 57911
* fix a tricky bug in the JIT global variable emitter, that was triggered when ↵Nuno Lopes2008-10-212-6/+40
| | | | | | JITing a variable independently of a function. This lead to sharing memory memory between functions and GVs thus changing the value of a GV could change the code in execution. more details on the ML. llvm-svn: 57900
* Disable constant-offset folding for PowerPC, as the PowerPC targetDan Gohman2008-10-212-0/+8
| | | | | | isn't yet prepared for it. llvm-svn: 57886
* Don't create TargetGlobalAddress nodes with offsets that don't fitDan Gohman2008-10-212-2/+2
| | | | | | | | | | | | | | in the 32-bit signed offset field of addresses. Even though this may be intended, some linkers refuse to relocate code where the relocated address computation overflows. Also, fix the sign-extension of constant offsets to use the actual pointer size, rather than the size of the GlobalAddress node, which may be different, for example on x86-64 where MVT::i32 is used when the address is being fit into the 32-bit displacement field. llvm-svn: 57885
* Optimized FCMP_OEQ and FCMP_UNE for x86.Dan Gohman2008-10-214-101/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
* When the coalescer is doing rematerializing, have it removeDan Gohman2008-10-212-5/+11
| | | | | | | | | | | | | | | | | | | | the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
* Make the NaN test come second, heuristically assumingDan Gohman2008-10-211-12/+12
| | | | | | that NaNs are less common. llvm-svn: 57871
* Use Function::getEntryBlock() instead of Function::front(), for clarity.Dan Gohman2008-10-211-1/+1
| | | | llvm-svn: 57870
* CMake: updated lib/CodeGen/CMakeLists.txtOscar Fuentes2008-10-211-0/+1
| | | | llvm-svn: 57869
* Fix a bug that prevented llvm-extract -delete from working.Dan Gohman2008-10-211-1/+1
| | | | llvm-svn: 57864
* Fix gcc.c-torture/compile/920520-1.c by inserting bitconvertsChris Lattner2008-10-211-7/+30
| | | | | | | | | for strange asm conditions earlier. In this case, we have a double being passed in an integer reg class. Convert to like sized integer register so that we allocate the right number for the class (two i32's for the f64 in this case). llvm-svn: 57862
* Add skeleton for the pre-register allocation live interval splitting pass.Evan Cheng2008-10-201-0/+81
| | | | llvm-svn: 57847
* Update the stub and callback code to handle lazy compilation. The stubJim Grosbach2008-10-203-64/+120
| | | | | | | | | | is re-written by the callback to branch directly to the compiled code in future invocations. Added back in range-based memory permission functions for the updating of the stub on Darwin. llvm-svn: 57846
* Fast-isel no longer an experiment.Dan Gohman2008-10-201-1/+1
| | | | llvm-svn: 57845
* Add a register class -> virtual registers map.Evan Cheng2008-10-201-0/+1
| | | | llvm-svn: 57844
* Support operations like fp_to_uint with a vectorDuncan Sands2008-10-202-1/+53
| | | | | | | | | result type when the result type is legal but not the operand type. Add additional support for EXTRACT_SUBVECTOR and CONCAT_VECTORS, needed to handle such cases. llvm-svn: 57840
* LegalizeTypes support for atomic operation promotion.Duncan Sands2008-10-202-3/+78
| | | | llvm-svn: 57838
* Use DAG.getIntPtrConstant rather than DAG.getConstantDuncan Sands2008-10-202-6/+4
| | | | | | with TLI.getPointerTy for a small simplification. llvm-svn: 57837
* Always use either MVT::i1 or getSetCCResultType forDuncan Sands2008-10-201-15/+51
| | | | | | | | the condition of a SELECT node. Make sure that the correct extension type (any-, sign- or zero-extend) is used. llvm-svn: 57836
* Formatting - no functional change.Duncan Sands2008-10-202-7/+6
| | | | llvm-svn: 57834
* Don't use a random type for the select condition,Duncan Sands2008-10-201-2/+1
| | | | | | use an MVT::i1 and simplify the code while there. llvm-svn: 57833
* Have X86 custom lowering for LegalizeTypes useDuncan Sands2008-10-201-10/+12
| | | | | | | | | | | | | LowerOperation if it doesn't know what else to do. This methods should probably be factorized some, but this is good enough for the moment. Have LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather than assuming the operand is a BUILD_PAIR (if it is then getNode will automagically simplify the EXTRACT_ELEMENT). This way LowerATOMIC_BINARY_64 usable from LegalizeTypes. llvm-svn: 57831
* Set N->OperandList to 0 after deletion. Otherwise, it's possible that it willBill Wendling2008-10-191-15/+26
| | | | | | be either deleted or referenced afterwards. llvm-svn: 57786
* Fix comment. Other formatting changes. No functionality changes.Bill Wendling2008-10-191-5/+6
| | | | llvm-svn: 57785
* Vector shuffle mask elements may be "undef". HandleDuncan Sands2008-10-191-13/+24
| | | | | | this everywhere in LegalizeTypes. llvm-svn: 57783
* Use a legal integer type for vector shuffle maskDuncan Sands2008-10-191-4/+4
| | | | | | | | | elements. Otherwise LegalizeTypes will, reasonably enough, legalize the mask, which may result in it no longer being a BUILD_VECTOR node (LegalizeDAG simply ignores the legality or not of vector masks). llvm-svn: 57782
* Reapply r57699 with a fix to not crash on asms with multiple results. UnlikeChris Lattner2008-10-181-16/+48
| | | | | | | | | | the previous patch this one actually passes make check. "Fix PR2356 on PowerPC: if we have an input and output that are tied together that have different sizes (e.g. i32 and i64) make sure to reserve registers for the bigger operand." llvm-svn: 57771
* Don't truncate GlobalAddress offsets to int in debug output.Dan Gohman2008-10-182-2/+2
| | | | llvm-svn: 57770
* By min, I mean max.Evan Cheng2008-10-181-1/+1
| | | | llvm-svn: 57766
* When creating intervals, leave min(1, numdefs) holes after each instruction.Evan Cheng2008-10-181-5/+13
| | | | llvm-svn: 57765
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-1815-72/+141
| | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
* Revert r57699. It's causing regressions inDan Gohman2008-10-181-43/+15
| | | | | | | test/CodeGen/X86/2008-09-17-inline-asm-1.ll and a few others, and it breaks the llvm-gcc build. llvm-svn: 57747
* This is now partly done.Dan Gohman2008-10-171-1/+1
| | | | llvm-svn: 57734
* This is done.Dan Gohman2008-10-171-10/+0
| | | | llvm-svn: 57733
* Factor out the code for mapping LLVM IR condition opcodes toDan Gohman2008-10-172-34/+47
| | | | | | ISD condition opcodes into helper functions. llvm-svn: 57726
* Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this ↵Evan Cheng2008-10-171-1/+2
| | | | | | is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file. llvm-svn: 57723
* Fix PR2898. Spiller delete a store for reuse before it knows for sure the ↵Evan Cheng2008-10-171-11/+26
| | | | | | | | reuse happened. Patch by Lang Hames! llvm-svn: 57720
* add support for 128 bit aggregates.Chris Lattner2008-10-171-0/+1
| | | | llvm-svn: 57715
* The Dwarf writer was comparing mangled and unmangled names for C++ code when weBill Wendling2008-10-171-1/+4
| | | | | | | | | have an unreachable block in a function. This was triggering the assert. This is a horrid hack to cover this up. Oh! for a good debug info architecture! llvm-svn: 57714
* Added MemIntrinsicNode which is useful to represent target intrinsics thatMon P Wang2008-10-171-2/+59
| | | | | | touches memory and need an associated MemOperand llvm-svn: 57712
* Factor out the code for mapping LLVM IR condition opcodes toDan Gohman2008-10-171-126/+61
| | | | | | ISD condition opcodes into helper functions. llvm-svn: 57710
OpenPOWER on IntegriCloud