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| author | Duncan Sands <baldrick@free.fr> | 2008-10-19 14:58:05 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-10-19 14:58:05 +0000 |
| commit | c6d12bd66583b6a732d4788d3559ffa0fc329d32 (patch) | |
| tree | 74babb9bcd237227c6513a3866ac7bd246a111c3 /llvm/lib | |
| parent | 455b973d333f25a7feeda235fca3a65a3377db01 (diff) | |
| download | bcm5719-llvm-c6d12bd66583b6a732d4788d3559ffa0fc329d32.tar.gz bcm5719-llvm-c6d12bd66583b6a732d4788d3559ffa0fc329d32.zip | |
Use a legal integer type for vector shuffle mask
elements. Otherwise LegalizeTypes will, reasonably
enough, legalize the mask, which may result in it
no longer being a BUILD_VECTOR node (LegalizeDAG
simply ignores the legality or not of vector masks).
llvm-svn: 57782
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 81058152eb0..0622c552d5a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5134,24 +5134,24 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { std::vector<SDValue> IdxOps; unsigned NumOps = RHS.getNumOperands(); unsigned NumElts = NumOps; - MVT EVT = RHS.getValueType().getVectorElementType(); for (unsigned i = 0; i != NumElts; ++i) { SDValue Elt = RHS.getOperand(i); if (!isa<ConstantSDNode>(Elt)) return SDValue(); else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) - IdxOps.push_back(DAG.getConstant(i, EVT)); + IdxOps.push_back(DAG.getIntPtrConstant(i)); else if (cast<ConstantSDNode>(Elt)->isNullValue()) - IdxOps.push_back(DAG.getConstant(NumElts, EVT)); + IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); else return SDValue(); } // Let's see if the target supports this vector_shuffle. - if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) + if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) return SDValue(); // Return the new VECTOR_SHUFFLE node. + MVT EVT = RHS.getValueType().getVectorElementType(); MVT VT = MVT::getVectorVT(EVT, NumElts); std::vector<SDValue> Ops; LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); |

